From owner-svn-src-all@FreeBSD.ORG Tue May 18 04:02:34 2010 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id B1C1C1065678; Tue, 18 May 2010 04:02:34 +0000 (UTC) (envelope-from rrs@FreeBSD.org) Received: from svn.freebsd.org (unknown [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 9F81F8FC14; Tue, 18 May 2010 04:02:34 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o4I42Y97033212; Tue, 18 May 2010 04:02:34 GMT (envelope-from rrs@svn.freebsd.org) Received: (from rrs@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o4I42Yew033206; Tue, 18 May 2010 04:02:34 GMT (envelope-from rrs@svn.freebsd.org) Message-Id: <201005180402.o4I42Yew033206@svn.freebsd.org> From: Randall Stewart Date: Tue, 18 May 2010 04:02:34 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r208249 - in head/sys/mips: include mips rmi sibyte X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 May 2010 04:02:34 -0000 Author: rrs Date: Tue May 18 04:02:34 2010 New Revision: 208249 URL: http://svn.freebsd.org/changeset/base/208249 Log: Adds JC's cleanup patches that fix it so we call an platform dependant topo function as well as clean up all the XLR specific ifdefs around smp platform init. Obtained from: JC Modified: head/sys/mips/include/hwfunc.h head/sys/mips/mips/mp_machdep.c head/sys/mips/mips/mpboot.S head/sys/mips/rmi/xlr_machdep.c head/sys/mips/sibyte/sb_machdep.c Modified: head/sys/mips/include/hwfunc.h ============================================================================== --- head/sys/mips/include/hwfunc.h Tue May 18 03:16:02 2010 (r208248) +++ head/sys/mips/include/hwfunc.h Tue May 18 04:02:34 2010 (r208249) @@ -93,5 +93,11 @@ extern int platform_processor_id(void); */ extern int platform_num_processors(void); +/* + * Return the topology of processors on this platform + */ +struct cpu_group *platform_smp_topo(void); + + #endif /* SMP */ #endif /* !_MACHINE_HWFUNC_H_ */ Modified: head/sys/mips/mips/mp_machdep.c ============================================================================== --- head/sys/mips/mips/mp_machdep.c Tue May 18 03:16:02 2010 (r208248) +++ head/sys/mips/mips/mp_machdep.c Tue May 18 04:02:34 2010 (r208249) @@ -196,8 +196,7 @@ cpu_mp_announce(void) struct cpu_group * cpu_topo(void) { - - return (smp_topo_none()); + return (platform_smp_topo()); } int @@ -238,10 +237,6 @@ cpu_mp_start(void) void smp_init_secondary(u_int32_t cpuid) { -#ifndef TARGET_XLR_XLS - int ipi_int_mask, clock_int_mask; -#endif - /* TLB */ Mips_SetWIRED(0); Mips_TLBFlush(num_tlbentries); @@ -294,17 +289,6 @@ smp_init_secondary(u_int32_t cpuid) while (smp_started == 0) ; /* nothing */ -#ifndef TARGET_XLR_XLS - /* - * Unmask the clock and ipi interrupts. - */ - clock_int_mask = hard_int_mask(5); - ipi_int_mask = hard_int_mask(platform_ipi_intrnum()); - set_intr_mask(ALL_INT_MASK & ~(ipi_int_mask | clock_int_mask)); -#else - platform_init_ap(cpuid); -#endif - /* * Bootstrap the compare register. */ Modified: head/sys/mips/mips/mpboot.S ============================================================================== --- head/sys/mips/mips/mpboot.S Tue May 18 03:16:02 2010 (r208248) +++ head/sys/mips/mips/mpboot.S Tue May 18 04:02:34 2010 (r208249) @@ -76,10 +76,8 @@ GLOBAL(mpentry) PTR_LA gp, _C_LABEL(_gp) -#ifndef TARGET_XLR_XLS jal platform_init_ap move a0, s0 -#endif jal smp_init_secondary move a0, s0 Modified: head/sys/mips/rmi/xlr_machdep.c ============================================================================== --- head/sys/mips/rmi/xlr_machdep.c Tue May 18 03:16:02 2010 (r208248) +++ head/sys/mips/rmi/xlr_machdep.c Tue May 18 04:02:34 2010 (r208249) @@ -534,6 +534,8 @@ void platform_init_ap(int processor_id) /* Setup interrupts for secondary CPUs here */ stat = mips_rd_status(); + KASSERT((stat & MIPS_SR_INT_IE) == 0, + ("Interrupts enabled in %s!", __func__)); stat |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT; mips_wr_status(stat); @@ -570,4 +572,11 @@ int platform_num_processors(void) { return fls(xlr_boot1_info.cpu_online_map); } + +struct cpu_group * +platform_smp_topo() +{ + return (smp_topo_2level(CG_SHARE_L2, platform_num_processors() / 4, + CG_SHARE_L1, 4, CG_FLAG_THREAD)); +} #endif Modified: head/sys/mips/sibyte/sb_machdep.c ============================================================================== --- head/sys/mips/sibyte/sb_machdep.c Tue May 18 03:16:02 2010 (r208248) +++ head/sys/mips/sibyte/sb_machdep.c Tue May 18 04:02:34 2010 (r208249) @@ -344,9 +344,16 @@ platform_ipi_intrnum(void) return (4); } +struct cpu_group * +platform_smp_topo(void) +{ + return (smp_topo_none()); +} + void platform_init_ap(int cpuid) { + int ipi_int_mask, clock_int_mask; KASSERT(cpuid == 1, ("AP has an invalid cpu id %d", cpuid)); @@ -356,6 +363,13 @@ platform_init_ap(int cpuid) kseg0_map_coherent(); sb_intr_init(cpuid); + + /* + * Unmask the clock and ipi interrupts. + */ + clock_int_mask = hard_int_mask(5); + ipi_int_mask = hard_int_mask(platform_ipi_intrnum()); + set_intr_mask(ALL_INT_MASK & ~(ipi_int_mask | clock_int_mask)); } int