From owner-svn-src-all@freebsd.org Tue May 12 01:36:48 2020 Return-Path: Delivered-To: svn-src-all@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id BFB242DE07A; Tue, 12 May 2020 01:36:48 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 49LgQ84d7gz4W69; Tue, 12 May 2020 01:36:48 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 99CFB27E89; Tue, 12 May 2020 01:36:48 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 04C1amlF097851; Tue, 12 May 2020 01:36:48 GMT (envelope-from adrian@FreeBSD.org) Received: (from adrian@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 04C1am6u097850; Tue, 12 May 2020 01:36:48 GMT (envelope-from adrian@FreeBSD.org) Message-Id: <202005120136.04C1am6u097850@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: adrian set sender to adrian@FreeBSD.org using -f From: Adrian Chadd Date: Tue, 12 May 2020 01:36:48 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r360950 - head/tools/tools/ath/ath_ee_9300_print X-SVN-Group: head X-SVN-Commit-Author: adrian X-SVN-Commit-Paths: head/tools/tools/ath/ath_ee_9300_print X-SVN-Commit-Revision: 360950 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.33 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 May 2020 01:36:48 -0000 Author: adrian Date: Tue May 12 01:36:48 2020 New Revision: 360950 URL: https://svnweb.freebsd.org/changeset/base/360950 Log: [ar9300] Update the ar9300 eeprom dump utility to include target power and CTL. This lets me easily see what the EEPROM target power and regulatory compliance table limits are. (Yeah, should've done this in 2013..) Modified: head/tools/tools/ath/ath_ee_9300_print/main.c Modified: head/tools/tools/ath/ath_ee_9300_print/main.c ============================================================================== --- head/tools/tools/ath/ath_ee_9300_print/main.c Tue May 12 01:23:05 2020 (r360949) +++ head/tools/tools/ath/ath_ee_9300_print/main.c Tue May 12 01:36:48 2020 (r360950) @@ -37,6 +37,34 @@ struct ath_hal; #include "ar9300/ar9300eep.h" +static const char * +eeprom_9300_ctl_idx_to_mode(uint8_t idx) +{ + switch (idx & 0xf) { + /* 2G CTLs */ + case 1: return "CCK"; + case 2: return "OFDM"; + case 5: return "HT20"; + case 7: return "HT40"; + /* 5G CTLs */ + case 0: return "OFDM"; + case 6: return "HT20"; + case 8: return "HT40"; + default: return ""; + } +} + +static const char * +eeprom_9300_ctl_idx_to_regdomain(uint8_t idx) +{ + switch (idx & 0xf0) { + case 0x10: return "FCC"; + case 0x30: return "ETSI"; + case 0x40: return "JP"; + } +} + + static void eeprom_9300_hdr_print(const uint16_t *buf) { @@ -156,6 +184,246 @@ eeprom_9300_modal_print(const OSPREY_MODAL_EEP_HEADER } static void +eeprom_9300_print_2g_target_cck(const ar9300_eeprom_t *ee) +{ + int i; + + for (i = 0; i < OSPREY_NUM_2G_CCK_TARGET_POWERS; i++) { + printf("| Freq %u CCK: pow2x 1/5L %u 5S %u 11L %u 11S %u\n", + FBIN2FREQ(ee->cal_target_freqbin_cck[i], 1), + ee->cal_target_power_cck[i].t_pow2x[LEGACY_TARGET_RATE_1L_5L], + ee->cal_target_power_cck[i].t_pow2x[LEGACY_TARGET_RATE_5S], + ee->cal_target_power_cck[i].t_pow2x[LEGACY_TARGET_RATE_11L], + ee->cal_target_power_cck[i].t_pow2x[LEGACY_TARGET_RATE_11S]); + } +} + +static void +eeprom_9300_print_2g_target_ofdm(const ar9300_eeprom_t *ee) +{ + int i; + + for (i = 0; i < OSPREY_NUM_2G_20_TARGET_POWERS; i++) { + printf("| Freq %u OFDM: pow2x 6/12/18/24M %u 36M %u 48M %u 54M %u\n", + FBIN2FREQ(ee->cal_target_freqbin_2g[i], 1), + ee->cal_target_power_2g[i].t_pow2x[LEGACY_TARGET_RATE_6_24], + ee->cal_target_power_2g[i].t_pow2x[LEGACY_TARGET_RATE_36], + ee->cal_target_power_2g[i].t_pow2x[LEGACY_TARGET_RATE_48], + ee->cal_target_power_2g[i].t_pow2x[LEGACY_TARGET_RATE_54]); + } +} + +static void +eeprom_9300_print_2g_target_ht20(const ar9300_eeprom_t *ee) +{ + int i; + + for (i = 0; i < OSPREY_NUM_2G_20_TARGET_POWERS; i++) { + printf("| Freq %u HT20 MCS0-7 pow2x %u %u %u %u %u %u %u %u %u\n", + FBIN2FREQ(ee->cal_target_freqbin_2g_ht20[i], 1), + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_0_8_16], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_4], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_5], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_6], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_7]); + printf("| Freq %u HT20 MCS8-15 pow2x %u %u %u %u %u %u %u %u %u\n", + FBIN2FREQ(ee->cal_target_freqbin_2g_ht20[i], 1), + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_0_8_16], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_12], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_13], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_14], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_15]); + printf("| Freq %u HT20 MCS16-23 pow2x %u %u %u %u %u %u %u %u %u\n", + FBIN2FREQ(ee->cal_target_freqbin_2g_ht20[i], 1), + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_0_8_16], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_20], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_21], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_22], + ee->cal_target_power_2g_ht20[i].t_pow2x[HT_TARGET_RATE_23]); + } +} + +static void +eeprom_9300_print_2g_target_ht40(const ar9300_eeprom_t *ee) +{ + int i; + + for (i = 0; i < OSPREY_NUM_2G_40_TARGET_POWERS; i++) { + printf("| Freq %u HT40 MCS0-7 pow2x %u %u %u %u %u %u %u %u %u\n", + FBIN2FREQ(ee->cal_target_freqbin_2g_ht40[i], 1), + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_0_8_16], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_4], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_5], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_6], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_7]); + printf("| Freq %u HT40 MCS8-15 pow2x %u %u %u %u %u %u %u %u %u\n", + FBIN2FREQ(ee->cal_target_freqbin_2g_ht40[i], 1), + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_0_8_16], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_12], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_13], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_14], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_15]); + printf("| Freq %u HT40 MCS16-23 pow2x %u %u %u %u %u %u %u %u %u\n", + FBIN2FREQ(ee->cal_target_freqbin_2g_ht40[i], 1), + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_0_8_16], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_20], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_21], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_22], + ee->cal_target_power_2g_ht40[i].t_pow2x[HT_TARGET_RATE_23]); + } +} + +static void +eeprom_9300_print_2g_ctls(const ar9300_eeprom_t *ee) +{ + int i, j; + + for (i = 0; i < OSPREY_NUM_CTLS_2G; i++) { + printf("| CTL index 0x%.02x (%s %s)\n", + ee->ctl_index_2g[i], + eeprom_9300_ctl_idx_to_regdomain(ee->ctl_index_2g[i]), + eeprom_9300_ctl_idx_to_mode(ee->ctl_index_2g[i])); + for (j = 0; j < OSPREY_NUM_BAND_EDGES_2G; j++) { + printf("| Freq %u pow2x %u flags 0x%x\n", + FBIN2FREQ(ee->ctl_freqbin_2G[i][j], 1), + ee->ctl_power_data_2g[i].ctl_edges[j].t_power, + ee->ctl_power_data_2g[i].ctl_edges[j].flag); + } + printf("\n"); + } +} + +static void +eeprom_9300_print_5g_target_ofdm(const ar9300_eeprom_t *ee) +{ + int i; + + for (i = 0; i < OSPREY_NUM_5G_20_TARGET_POWERS; i++) { + printf("| Freq %u OFDM: pow2x 6/12/18/24M %u 36M %u 48M %u 54M %u\n", + FBIN2FREQ(ee->cal_target_freqbin_5g[i], 0), + ee->cal_target_power_5g[i].t_pow2x[LEGACY_TARGET_RATE_6_24], + ee->cal_target_power_5g[i].t_pow2x[LEGACY_TARGET_RATE_36], + ee->cal_target_power_5g[i].t_pow2x[LEGACY_TARGET_RATE_48], + ee->cal_target_power_5g[i].t_pow2x[LEGACY_TARGET_RATE_54]); + } +} + +static void +eeprom_9300_print_5g_target_ht20(const ar9300_eeprom_t *ee) +{ + int i; + + for (i = 0; i < OSPREY_NUM_5G_20_TARGET_POWERS; i++) { + printf("| Freq %u HT20 MCS0-7 pow2x %u %u %u %u %u %u %u %u\n", + FBIN2FREQ(ee->cal_target_freqbin_5g_ht20[i], 0), + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_0_8_16], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_4], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_5], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_6], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_7]); + printf("| Freq %u HT20 MCS8-15 pow2x %u %u %u %u %u %u %u %u\n", + FBIN2FREQ(ee->cal_target_freqbin_5g_ht20[i], 0), + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_0_8_16], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_12], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_13], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_14], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_15]); + printf("| Freq %u HT20 MCS16-23 pow2x %u %u %u %u %u %u %u %u\n", + FBIN2FREQ(ee->cal_target_freqbin_5g_ht20[i], 0), + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_0_8_16], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_20], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_21], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_22], + ee->cal_target_power_5g_ht20[i].t_pow2x[HT_TARGET_RATE_23]); + } +} + +static void +eeprom_9300_print_5g_target_ht40(const ar9300_eeprom_t *ee) +{ + int i; + + for (i = 0; i < OSPREY_NUM_5G_40_TARGET_POWERS; i++) { + printf("| Freq %u HT40 MCS0-7 pow2x %u %u %u %u %u %u %u %u\n", + FBIN2FREQ(ee->cal_target_freqbin_5g_ht40[i], 0), + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_0_8_16], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_4], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_5], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_6], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_7]); + printf("| Freq %u HT40 MCS8-15 pow2x %u %u %u %u %u %u %u %u\n", + FBIN2FREQ(ee->cal_target_freqbin_5g_ht40[i], 0), + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_0_8_16], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_12], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_13], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_14], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_15]); + printf("| Freq %u HT40 MCS16-23 pow2x %u %u %u %u %u %u %u %u\n", + FBIN2FREQ(ee->cal_target_freqbin_5g_ht40[i], 0), + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_0_8_16], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_1_3_9_11_17_19], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_20], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_21], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_22], + ee->cal_target_power_5g_ht40[i].t_pow2x[HT_TARGET_RATE_23]); + } +} + +static void +eeprom_9300_print_5g_ctls(const ar9300_eeprom_t *ee) +{ + int i, j; + + for (i = 0; i < OSPREY_NUM_CTLS_5G; i++) { + printf("| CTL index 0x%.02x (%s %s)\n", ee->ctl_index_5g[i], + eeprom_9300_ctl_idx_to_regdomain(ee->ctl_index_5g[i]), + eeprom_9300_ctl_idx_to_mode(ee->ctl_index_5g[i])); + for (j = 0; j < OSPREY_NUM_BAND_EDGES_5G; j++) { + printf("| Freq %u pow2x %u Flags 0x%x\n", + FBIN2FREQ(ee->ctl_freqbin_5G[i][j], 0), + ee->ctl_power_data_5g[i].ctl_edges[j].t_power, + ee->ctl_power_data_5g[i].ctl_edges[j].flag); + } + printf("\n"); + } +} + +static void load_eeprom_dump(const char *file, uint16_t *buf) { unsigned int r[8]; @@ -222,9 +490,19 @@ main(int argc, char *argv[]) printf("\n2GHz modal:\n"); eeprom_9300_modal_print(&ee->modal_header_2g); + // TODO: open-loop calibration + eeprom_9300_print_2g_target_cck(ee); + eeprom_9300_print_2g_target_ofdm(ee); + eeprom_9300_print_2g_target_ht20(ee); + eeprom_9300_print_2g_target_ht40(ee); + eeprom_9300_print_2g_ctls(ee); printf("\n5GHz modal:\n"); eeprom_9300_modal_print(&ee->modal_header_5g); + eeprom_9300_print_5g_target_ofdm(ee); + eeprom_9300_print_5g_target_ht20(ee); + eeprom_9300_print_5g_target_ht40(ee); + eeprom_9300_print_5g_ctls(ee); free(eep); exit(0);