From owner-svn-src-projects@FreeBSD.ORG Sun Jul 5 15:19:28 2009 Return-Path: Delivered-To: svn-src-projects@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id CF38A106564A; Sun, 5 Jul 2009 15:19:28 +0000 (UTC) (envelope-from imp@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id BE9448FC16; Sun, 5 Jul 2009 15:19:28 +0000 (UTC) (envelope-from imp@FreeBSD.org) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n65FJSj2052835; Sun, 5 Jul 2009 15:19:28 GMT (envelope-from imp@svn.freebsd.org) Received: (from imp@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n65FJSVU052833; Sun, 5 Jul 2009 15:19:28 GMT (envelope-from imp@svn.freebsd.org) Message-Id: <200907051519.n65FJSVU052833@svn.freebsd.org> From: Warner Losh Date: Sun, 5 Jul 2009 15:19:28 +0000 (UTC) To: src-committers@freebsd.org, svn-src-projects@freebsd.org X-SVN-Group: projects MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r195369 - projects/mips/sys/mips/include X-BeenThere: svn-src-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the src " projects" tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 05 Jul 2009 15:19:29 -0000 Author: imp Date: Sun Jul 5 15:19:28 2009 New Revision: 195369 URL: http://svn.freebsd.org/changeset/base/195369 Log: The SB1 needs a special value for the cache field of the pte. Submitted by: Neelkanth Natu Modified: projects/mips/sys/mips/include/pte.h Modified: projects/mips/sys/mips/include/pte.h ============================================================================== --- projects/mips/sys/mips/include/pte.h Sun Jul 5 15:18:06 2009 (r195368) +++ projects/mips/sys/mips/include/pte.h Sun Jul 5 15:19:28 2009 (r195369) @@ -105,7 +105,11 @@ typedef pt_entry_t *pd_entry_t; #define PTE_ODDPG 0x00001000 /*#define PG_ATTR 0x0000003f Not Used */ #define PTE_UNCACHED 0x00000010 +#ifdef CPU_SB1 +#define PTE_CACHE 0x00000028 /* cacheable coherent */ +#else #define PTE_CACHE 0x00000018 +#endif /*#define PG_CACHEMODE 0x00000038 Not Used*/ #define PTE_ROPAGE (PTE_V | PTE_RO | PTE_CACHE) /* Write protected */ #define PTE_RWPAGE (PTE_V | PTE_M | PTE_CACHE) /* Not wr-prot not clean */