From owner-freebsd-questions Thu Mar 7 14:53:43 1996 Return-Path: owner-questions Received: (from root@localhost) by freefall.freebsd.org (8.7.3/8.7.3) id OAA28416 for questions-outgoing; Thu, 7 Mar 1996 14:53:43 -0800 (PST) Received: from ns.okbmei.msk.su (ns.okbmei.msk.su [194.190.170.40]) by freefall.freebsd.org (8.7.3/8.7.3) with SMTP id OAA28351 for ; Thu, 7 Mar 1996 14:53:34 -0800 (PST) Received: from kiae.UUCP by ns.okbmei.msk.su with UUCP id AA29289 (5.67c8/IDA-1.5); Fri, 8 Mar 1996 01:40:51 +0300 Received: from freefall.FreeBSD.ORG by sequent.kiae.su with SMTP id AA21603 (5.65.kiae-2 for ); Fri, 8 Mar 1996 01:34:27 +0300 Received: from localhost (daemon@localhost) by freefall.freebsd.org (8.7.3/8.7.3) with SMTP id MAA07696 Thu, 7 Mar 1996 12:54:40 -0800 (PST) Received: (from root@localhost) by freefall.freebsd.org (8.7.3/8.7.3) id MAA07550 for questions-outgoing; Thu, 7 Mar 1996 12:52:52 -0800 (PST) Received: from phaeton.artisoft.com (phaeton.Artisoft.COM [198.17.250.211]) by freefall.freebsd.org (8.7.3/8.7.3) with SMTP id MAA07538 for ; Thu, 7 Mar 1996 12:52:49 -0800 (PST) Received: (from terry@localhost) by phaeton.artisoft.com (8.6.11/8.6.9) id NAA14745; Thu, 7 Mar 1996 13:47:20 -0700 From: Terry Lambert Message-Id: <199603072047.NAA14745@phaeton.artisoft.com> Subject: Re: Bad Ethernet cards To: luigi@labinfo.iet.unipi.it (Luigi Rizzo) Date: Thu, 7 Mar 1996 13:47:20 -0700 (MST) Cc: terry@lambert.org, wollman@lcs.mit.edu, questions@FreeBSD.ORG In-Reply-To: <199603071823.TAA11355@labinfo.iet.unipi.it> from "Luigi Rizzo" at Mar 7, 96 07:23:33 pm X-Mailer: ELM [version 2.4 PL24] Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Charset: KOI8-R X-Char-Esc: 29 Sender: owner-questions@FreeBSD.ORG Precedence: bulk > > You forget that it takes 4 CPU clocks for one PCI clock for a 133MHz > > P5. > > > > Multiply your PIO overhead by 4 (or more, if you trigger any wait > > states). > > I did my computation as follows: assume the CPU has to transfer 1MB/s > from the board. Say the available bandwidth on the PCI bus, doing > programmed I/O, is X MB/s. Then the CPU uses 1/X of its time just to > transfer that 1MB/s. For X=20, that makes 5% of the CPU time > unavailable for other things. Anything wrong ? The CPU spends 1/X * clock_differential_for_bus_access of its time; it will be in "bus wait" on clock_differential_for_bus_access - 1 of those clocks that it ordinarily would be using to run instructions in its L1 cache. > Now, the board in question has a single (it's a cheap unit!) 35ns > SRAM on it, which means that it can probably supply one byte every > 66ns (the closest multiple of the PCI period). That makes a BW of > 15 MB/s, not too far from my estimate. I don't doubt you could fully utilize the bus with programmed I/O. I just doubt that I/O binding the CPU is necessary, and I think the impact on the ability of the CPU to do useful work is multiplied by the clock_differential_for_bus_access -- on a P5 133, a factor of 4. I think that on most systems, the CPU has useful work to do other than accessing the I/O bus. I intensely dislike clock multiplied chips for precisely this reason; the differential is applied to the memory as well as the I/O bus. But applying it to the I/O bus in a PIO case multiplies the effect radically. PCI is, unfortunately, pretty well pegged at 33MHz. As CPU clock and memory speed goes up, the PIO problem will only get worse. Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers.