Date: Tue, 11 Apr 2023 11:45:54 +0000 From: Lee MATTHEWS <Lee.MATTHEWS.external@stormshield.eu> To: "freebsd-hackers@FreeBSD.org" <freebsd-hackers@FreeBSD.org> Subject: BINIT and BERR signals in MCA Message-ID: <4bd3e1017a104598ab92e658f25b5367@stormshield.eu>
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--_000_4bd3e1017a104598ab92e658f25b5367stormshieldeu_
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Hello,
One of our clients is experiencing problems using one of our products. It r=
uns FreeBSD 11.3 on an Intel Atom Apollo Lake E3930 two core SoC processor.
Occasionally, under very light load, the kernel will panic. I've managed to=
get a couple of vmcores and I notice via the backtrace that the MCA interr=
upt is called.
I've managed to recover two vmcores and I notice in both of them that the I=
nter-Processor Interrupts are not being transferred from one CPU to the oth=
er. I've also noticed that the structure mca_internal contains information =
concerning the state of the MCA status register (value : 0x9000000020000003=
) for bank 0.
>From Intel's software architecture document, the MCA Error Code is 0x0003 "=
The BINIT# from another processor caused this processor to enter machine ch=
eck." and the Model Specific Error Code is 0x2000 "1 if BERR is driven."
The Intel document is not clear; could anyone please explain what the BINIT=
and BERR signals mean? They appear to be related to a bus, but I'm not sur=
e which one. A bus external to the Atom SoC or one of the internal buses wi=
thin the Atom SoC?
Do you have any ideas of what could generate this type of error? Is it like=
ly a hardware or a software issue?
Thanks in advance.
Best wishes,
Lee Matthews
--_000_4bd3e1017a104598ab92e658f25b5367stormshieldeu_
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<div>Hello,<br>
<br>
One of our clients is experiencing problems using one of our products. It r=
uns FreeBSD 11.3 on an Intel Atom Apollo Lake E3930 two core SoC processor.=
<br>
<br>
Occasionally, under very light load, the kernel will panic. I've managed to=
get a couple of vmcores and I notice via the backtrace that the MCA interr=
upt is called.<br>
<br>
I've managed to recover two vmcores and I notice in both of them that the I=
nter-Processor Interrupts are not being transferred from one CPU to the oth=
er. I've also noticed that the structure mca_internal contains information =
concerning the state of the MCA
status register (value : 0x9000000020000003) for bank 0. <br>
<br>
>From Intel's software architecture document, the MCA Error Code is 0x0003 &=
quot;The BINIT# from another processor caused this processor to enter machi=
ne check." and the Model Specific Error Code is 0x2000 "1 if BERR=
is driven."<br>
<br>
The Intel document is not clear; could anyone please explain what the BINIT=
and BERR signals mean? They appear to be related to a bus, but I'm not sur=
e which one. A bus external to the Atom SoC or one of the internal buses wi=
thin the Atom SoC?<br>
<br>
Do you have any ideas of what could generate this type of error? Is it like=
ly a hardware or a software issue?<br>
<br>
Thanks in advance.<br>
</div>
<div><br>
</div>
<div>Best wishes,</div>
<div>Lee Matthews<br>
</div>
<br>
<p></p>
</div>
</body>
</html>
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