From owner-p4-projects@FreeBSD.ORG Tue Jun 19 16:04:48 2012 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 9B8FC106568F; Tue, 19 Jun 2012 16:04:48 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 5DC071065686 for ; Tue, 19 Jun 2012 16:04:48 +0000 (UTC) (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: from skunkworks.freebsd.org (skunkworks.freebsd.org [IPv6:2001:4f8:fff6::2d]) by mx1.freebsd.org (Postfix) with ESMTP id 445B98FC19 for ; Tue, 19 Jun 2012 16:04:48 +0000 (UTC) Received: from skunkworks.freebsd.org (localhost [127.0.0.1]) by skunkworks.freebsd.org (8.14.4/8.14.4) with ESMTP id q5JG4mOl035105 for ; Tue, 19 Jun 2012 16:04:48 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Received: (from perforce@localhost) by skunkworks.freebsd.org (8.14.4/8.14.4/Submit) id q5JG4mgb035102 for perforce@freebsd.org; Tue, 19 Jun 2012 16:04:48 GMT (envelope-from bb+lists.freebsd.perforce@cyrus.watson.org) Date: Tue, 19 Jun 2012 16:04:48 GMT Message-Id: <201206191604.q5JG4mgb035102@skunkworks.freebsd.org> X-Authentication-Warning: skunkworks.freebsd.org: perforce set sender to bb+lists.freebsd.perforce@cyrus.watson.org using -f From: Robert Watson To: Perforce Change Reviews Precedence: bulk Cc: Subject: PERFORCE change 213149 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Jun 2012 16:04:49 -0000 http://p4web.freebsd.org/@@213149?ac=10 Change 213149 by rwatson@rwatson_svr_ctsrd_mipsbuild on 2012/06/19 16:04:11 Tidy up of CHERI headers as we begin to create userspace BSD parts that use CHERI features (e.g., test tools): - Update header guards for renamed CHERI header files. - Protect kernel-specific definitions (and also CTASSERT()s) from userspace in CHERI headers. - Don't allow cheriasm.h to be usd from userspace as we don't currently need it there. Perhaps we will someday. Affected files ... .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#2 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheriasm.h#2 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cherireg.h#2 edit Differences ... ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#2 (text+ko) ==== @@ -28,10 +28,12 @@ * SUCH DAMAGE. */ -#ifndef _MIPS_CHERI_CP2_H_ -#define _MIPS_CHERI_CP2_H_ +#ifndef _MIPS_INCLUDE_CHERI_H_ +#define _MIPS_INCLUDE_CHERI_H_ +#ifdef _KERNEL #include /* CTASSERT */ +#endif #include @@ -49,7 +51,9 @@ uint64_t c_base; uint64_t c_length; } __packed __aligned(CAPABILITY_SIZE); +#ifdef _KERNEL CTASSERT(sizeof(struct capability) == CAPABILITY_SIZE); +#endif /* * Register frame to be preserved on context switching -- very similar to @@ -58,6 +62,7 @@ * * Must match the register offset definitions (CHERI_*_OFF) in cp2reg.h. */ +#ifdef _KERNEL struct cp2_frame { /* c0 has special properties for MIPS load/store instructions. */ struct capability cf_c0; @@ -86,6 +91,7 @@ struct capability cf_pcc; }; CTASSERT(sizeof(struct cp2_frame) == (28 * CAPABILITY_SIZE)); +#endif /* * CP2 capability register manipulation macros. @@ -318,9 +324,13 @@ void cp2_capability_set_upriv(struct capability *cp); void cp2_capability_set_null(struct capability *cp); +#ifdef _KERNEL +/* + * Kernel-specific CHERI context management functions. + */ void cp2_context_copy(struct cp2_frame *cf_destp, struct cp2_frame *cf_srcp); - void cheri_exec_setregs(struct thread *td); +#endif -#endif /* _MIPS_CHERI_CP2_H_ */ +#endif /* _MIPS_INCLUDE_CHERI_H_ */ ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheriasm.h#2 (text+ko) ==== @@ -28,8 +28,12 @@ * SUCH DAMAGE. */ -#ifndef _MIPS_CHERI_CP2ASM_H_ -#define _MIPS_CHERI_CP2ASM_H_ +#ifndef _MIPS_INCLUDE_CHERIASM_H_ +#define _MIPS_INCLUDE_CHERIASM_H_ + +#ifndef _KERNEL +#error "no user-serviceable parts inside" +#endif /* * Assembly code to be used in CHERI exception handling and context switching. @@ -147,4 +151,4 @@ RESTORE_U_PCB_CP2REG(treg, $c25, CHERI_CR_UDC_OFF, base); \ RESTORE_U_PCB_CP2REG(treg, $c28, CHERI_CR_TSC_OFF, base) -#endif /* _MIPS_CHERI_CP2ASM_H_ */ +#endif /* _MIPS_INCLUDE_CHERIASM_H_ */ ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cherireg.h#2 (text+ko) ==== @@ -28,8 +28,8 @@ * SUCH DAMAGE. */ -#ifndef _MIPS_CHERI_CP2REG_H_ -#define _MIPS_CHERI_CP2REG_H_ +#ifndef _MIPS_INCLUDE_CHERIREG_H_ +#define _MIPS_INCLUDE_CHERIREG_H_ /* * CHERI ISA-defined constants for capabilities -- suitable for inclusion from @@ -139,4 +139,4 @@ #define CHERI_CR_TSC_OFF 26 #define CHERI_CR_PC_OFF 27 -#endif /* _MIPS_CHERI_CP2REG_H_ */ +#endif /* _MIPS_INCLUDE_CHERIREG_H_ */