Date: Tue, 12 Jun 2018 16:19:27 +0000 (UTC) From: Ruslan Bukin <br@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r335000 - head/sys/riscv/riscv Message-ID: <201806121619.w5CGJRna083861@repo.freebsd.org>
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Author: br Date: Tue Jun 12 16:19:27 2018 New Revision: 335000 URL: https://svnweb.freebsd.org/changeset/base/335000 Log: Align virtual addressing entries. This is required due to C-compressed ISA extension option being turned on. This fixes SMP operation in QEMU. Sponsored by: DARPA, AFRL Modified: head/sys/riscv/riscv/locore.S Modified: head/sys/riscv/riscv/locore.S ============================================================================== --- head/sys/riscv/riscv/locore.S Tue Jun 12 14:54:17 2018 (r334999) +++ head/sys/riscv/riscv/locore.S Tue Jun 12 16:19:27 2018 (r335000) @@ -156,6 +156,8 @@ _start: or s2, s2, t0 sfence.vma csrw sptbr, s2 + + .align 2 va: /* Setup supervisor trap vector */ @@ -284,6 +286,8 @@ ENTRY(mpentry) or s2, s2, t0 sfence.vma csrw sptbr, s2 + + .align 2 mpva: /* Setup supervisor trap vector */ la t0, cpu_exception_handler
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