From owner-p4-projects@FreeBSD.ORG Sat Nov 1 12:45:13 2003 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 6939516A4D0; Sat, 1 Nov 2003 12:45:13 -0800 (PST) Delivered-To: perforce@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 42D4D16A4CE for ; Sat, 1 Nov 2003 12:45:13 -0800 (PST) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id 2272843F75 for ; Sat, 1 Nov 2003 12:45:12 -0800 (PST) (envelope-from jmallett@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.12.9/8.12.9) with ESMTP id hA1KjCXJ075241 for ; Sat, 1 Nov 2003 12:45:12 -0800 (PST) (envelope-from jmallett@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.12.9/8.12.9/Submit) id hA1KjBF8075238 for perforce@freebsd.org; Sat, 1 Nov 2003 12:45:11 -0800 (PST) (envelope-from jmallett@freebsd.org) Date: Sat, 1 Nov 2003 12:45:11 -0800 (PST) Message-Id: <200311012045.hA1KjBF8075238@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to jmallett@freebsd.org using -f From: Juli Mallett To: Perforce Change Reviews Subject: PERFORCE change 41076 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 01 Nov 2003 20:45:13 -0000 http://perforce.freebsd.org/chv.cgi?CH=41076 Change 41076 by jmallett@jmallett_dalek on 2003/11/01 12:44:05 Clean up warnings. Hackish in some places, a big improvement in others. Affected files ... .. //depot/projects/mips/sys/dev/arcbios/arcbios.c#9 edit .. //depot/projects/mips/sys/mips/include/asm.h#11 edit .. //depot/projects/mips/sys/mips/include/db_machdep.h#7 edit .. //depot/projects/mips/sys/mips/include/pmap.h#11 edit .. //depot/projects/mips/sys/mips/include/pte.h#11 edit .. //depot/projects/mips/sys/mips/include/tlb.h#2 edit .. //depot/projects/mips/sys/mips/mips/cache.c#5 edit .. //depot/projects/mips/sys/mips/mips/cache_r5k.c#4 edit .. //depot/projects/mips/sys/mips/mips/db_disasm.c#2 edit .. //depot/projects/mips/sys/mips/mips/db_interface.c#7 edit .. //depot/projects/mips/sys/mips/mips/db_trace.c#4 edit .. //depot/projects/mips/sys/mips/mips/locore_mips3.S#13 edit .. //depot/projects/mips/sys/mips/mips/machdep.c#34 edit .. //depot/projects/mips/sys/mips/mips/mips_subr.S#14 edit .. //depot/projects/mips/sys/mips/mips/pmap.c#18 edit .. //depot/projects/mips/sys/mips/mips/syscall.c#2 edit .. //depot/projects/mips/sys/mips/mips/tlb.c#5 edit .. //depot/projects/mips/sys/mips/mips/trap.c#9 edit .. //depot/projects/mips/sys/mips/sgimips/ip22.c#5 edit .. //depot/projects/mips/sys/mips/sgimips/machdep_sgimips.c#20 edit Differences ... ==== //depot/projects/mips/sys/dev/arcbios/arcbios.c#9 (text+ko) ==== @@ -139,7 +139,7 @@ static void arcbios_fill_vector(struct arcbios *A, const struct arcbios_fv *V) { -#define ARCSET(Func) A->Func = (void (*)(void))(int) V->Func +#define ARCSET(Func) A->Func = (void *)(intptr_t)(int) V->Func ARCSET(Load); ARCSET(Invoke); ARCSET(Execute); @@ -230,7 +230,7 @@ dstsize--; if (dstsize > node->IdentifierLength) dstsize = node->IdentifierLength; - memcpy(dst, MIPS_PHYS_TO_KSEG1(node->Identifier), dstsize); + memcpy(dst, (void *)MIPS_PHYS_TO_KSEG1(node->Identifier), dstsize); dst[dstsize] = '\0'; } @@ -245,7 +245,7 @@ arcbios_consdev.cn_dev = makedev(MAJOR_AUTO, 0); make_dev(&arcbios_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600, "arccons"); cnadd(&arcbios_consdev); - return (0); + return; } int ==== //depot/projects/mips/sys/mips/include/asm.h#11 (text+ko) ==== ==== //depot/projects/mips/sys/mips/include/db_machdep.h#7 (text+ko) ==== @@ -83,6 +83,7 @@ void kdb_kbd_trap(db_regs_t *); void db_set_ddb_regs(int type, struct trapframe *); int kdb_trap(int type, struct trapframe *); +int kdbpeek(db_addr_t); #define DB_SMALL_VALUE_MAX (0x7fffffff) #define DB_SMALL_VALUE_MIN (-0x40001) ==== //depot/projects/mips/sys/mips/include/pmap.h#11 (text+ko) ==== @@ -79,6 +79,8 @@ void pmap_bootstrap(void); vm_offset_t pmap_kextract(vm_offset_t); vm_offset_t pmap_steal_memory(vm_size_t); +void *pmap_mapdev(vm_offset_t, vm_size_t); +void pmap_unmapdev(vm_offset_t, vm_size_t); #define pmap_resident_count(pm) ((pm)->pm_stats.resident_count) #define vtophys(va) pmap_kextract((vm_offset_t)(va)) ==== //depot/projects/mips/sys/mips/include/pte.h#11 (text+ko) ==== @@ -67,12 +67,22 @@ * bit 12 to bit 8 there is a 5-bit 0 field. Low byte is ASID. */ #define MIPS_HI_R_SHIFT 62 +#ifdef LOCORE #define MIPS_HI_R_USER (0x00 << MIPS_HI_R_SHIFT) #define MIPS_HI_R_SUPERVISOR (0x01 << MIPS_HI_R_SHIFT) #define MIPS_HI_R_KERNEL (0x11 << MIPS_HI_R_SHIFT) +#else +#define MIPS_HI_R_USER (0x00UL << MIPS_HI_R_SHIFT) +#define MIPS_HI_R_SUPERVISOR (0x01UL << MIPS_HI_R_SHIFT) +#define MIPS_HI_R_KERNEL (0x11UL << MIPS_HI_R_SHIFT) +#endif #define MIPS_HI_FILL_SHIFT 40 #define MIPS_HI_VPN2_SHIFT 13 +#ifdef LOCORE #define MIPS_HI_VPN2_BMASK 0xFFFFFFE +#else +#define MIPS_HI_VPN2_BMASK 0xFFFFFFEUL +#endif #define MIPS_HI_VPN2_MASK (MIPS_HI_VPN2_BMASK << MIPS_HI_VPN2_SHIFT) #define MIPS_HI_VA_TO_VPN2(va) ((va) & MIPS_HI_VPN2_MASK) ==== //depot/projects/mips/sys/mips/include/tlb.h#2 (text+ko) ==== @@ -21,6 +21,7 @@ void tlb_bootstrap(vm_size_t, vm_offset_t (*)(vm_size_t)); void tlb_enter(pmap_t, vm_offset_t, vm_paddr_t, pt_entry_t); void tlb_invalidate_page(vm_offset_t); +void tlb_modified(void *); void tlb_remove(pmap_t, vm_offset_t); void tlb_remove_pages(pmap_t, vm_offset_t, int); void tlb_remove_range(pmap_t, vm_offset_t, vm_offset_t); ==== //depot/projects/mips/sys/mips/mips/cache.c#5 (text+ko) ==== @@ -727,9 +727,9 @@ break; #ifdef MIPS_DISABLE_L1_CACHE case 0: - mips_cache_ops.mco_icache_sync_all = (void *)cache_noop; - mips_cache_ops.mco_icache_sync_range = (void *)cache_noop; - mips_cache_ops.mco_icache_sync_range_index = (void *)cache_noop; + mips_cache_ops.mco_icache_sync_all = (void *)(uintptr_t)cache_noop; + mips_cache_ops.mco_icache_sync_range = (void *)(uintptr_t)cache_noop; + mips_cache_ops.mco_icache_sync_range_index = (void *)(uintptr_t)cache_noop; break; #endif default: @@ -770,17 +770,17 @@ break; #ifdef MIPS_DISABLE_L1_CACHE case 0: - mips_cache_ops.mco_pdcache_wbinv_all = (void *)cache_noop; + mips_cache_ops.mco_pdcache_wbinv_all = (void *)(uintptr_t)cache_noop; mips_cache_ops.mco_intern_pdcache_wbinv_all = - (void *)cache_noop; - mips_cache_ops.mco_pdcache_wbinv_range = (void *)cache_noop; + (void *)(uintptr_t)cache_noop; + mips_cache_ops.mco_pdcache_wbinv_range = (void *)(uintptr_t)cache_noop; mips_cache_ops.mco_pdcache_wbinv_range_index = - (void *)cache_noop; + (void *)(uintptr_t)cache_noop; mips_cache_ops.mco_intern_pdcache_wbinv_range_index = - (void *)cache_noop; - mips_cache_ops.mco_pdcache_inv_range = (void *)cache_noop; - mips_cache_ops.mco_pdcache_wb_range = (void *)cache_noop; - mips_cache_ops.mco_intern_pdcache_wb_range = (void *)cache_noop; + (void *)(uintptr_t)cache_noop; + mips_cache_ops.mco_pdcache_inv_range = (void *)(uintptr_t)cache_noop; + mips_cache_ops.mco_pdcache_wb_range = (void *)(uintptr_t)cache_noop; + mips_cache_ops.mco_intern_pdcache_wb_range = (void *)(uintptr_t)cache_noop; break; #endif default: @@ -795,22 +795,22 @@ #ifdef CACHE_DEBUG printf(" Dcache is coherent\n"); #endif - mips_cache_ops.mco_pdcache_wbinv_all = (void *)cache_noop; - mips_cache_ops.mco_pdcache_wbinv_range = (void *)cache_noop; + mips_cache_ops.mco_pdcache_wbinv_all = (void *)(uintptr_t)cache_noop; + mips_cache_ops.mco_pdcache_wbinv_range = (void *)(uintptr_t)cache_noop; mips_cache_ops.mco_pdcache_wbinv_range_index = - (void *)cache_noop; - mips_cache_ops.mco_pdcache_inv_range = (void *)cache_noop; - mips_cache_ops.mco_pdcache_wb_range = (void *)cache_noop; + (void *)(uintptr_t)cache_noop; + mips_cache_ops.mco_pdcache_inv_range = (void *)(uintptr_t)cache_noop; + mips_cache_ops.mco_pdcache_wb_range = (void *)(uintptr_t)cache_noop; } if (mips_cpu_flags & CPU_MIPS_I_D_CACHE_COHERENT) { #ifdef CACHE_DEBUG printf(" Icache is coherent against Dcache\n"); #endif mips_cache_ops.mco_intern_pdcache_wbinv_all = - (void *)cache_noop; + (void *)(uintptr_t)cache_noop; mips_cache_ops.mco_intern_pdcache_wbinv_range_index = - (void *)cache_noop; + (void *)(uintptr_t)cache_noop; mips_cache_ops.mco_intern_pdcache_wb_range = - (void *)cache_noop; + (void *)(uintptr_t)cache_noop; } } ==== //depot/projects/mips/sys/mips/mips/cache_r5k.c#4 (text+ko) ==== @@ -618,9 +618,6 @@ r5k_sdcache_wbinv_all(); } -#define round_page(x) (((x) + (128 * 32 - 1)) & ~(128 * 32 - 1)) -#define trunc_page(x) ((x) & ~(128 * 32 - 1)) - void r5k_sdcache_wbinv_range(vm_paddr_t va, vm_size_t size) { ==== //depot/projects/mips/sys/mips/mips/db_disasm.c#2 (text+ko) ==== @@ -498,8 +498,8 @@ print_addr(db_addr_t loc) { db_expr_t diff; - db_sym_t sym; - char *symname; + c_db_sym_t sym; + const char *symname; diff = INT_MAX; symname = NULL; ==== //depot/projects/mips/sys/mips/mips/db_interface.c#7 (text+ko) ==== @@ -35,6 +35,7 @@ #include #include #include +#include #include #include @@ -179,13 +180,6 @@ } void -cpu_Debugger(void) -{ - - __asm("break"); -} - -void db_set_ddb_regs(int type, struct trapframe *tfp) { struct frame *f = (struct frame *)&ddb_regs; @@ -292,12 +286,12 @@ db_printf("TLB%c%2d Hi 0x%016lx ", (tlb.tlb_lo0 | tlb.tlb_lo1) & PG_V ? ' ' : '*', i, tlb.tlb_hi); - db_printf("Lo0=0x%016lx %c%c attr %x ", + db_printf("Lo0=0x%016lx %c%c attr %lx ", MIPS_PFN_TO_PA(tlb.tlb_lo0), (tlb.tlb_lo0 & PG_D) ? 'D' : ' ', (tlb.tlb_lo0 & PG_G) ? 'G' : ' ', (tlb.tlb_lo0 >> 3) & 7); - db_printf("Lo1=0x%016lx %c%c attr %x sz=%x\n", + db_printf("Lo1=0x%016lx %c%c attr %lx sz=%x\n", MIPS_PFN_TO_PA(tlb.tlb_lo1), (tlb.tlb_lo1 & PG_D) ? 'D' : ' ', (tlb.tlb_lo1 & PG_G) ? 'G' : ' ', @@ -332,7 +326,7 @@ \ __asm __volatile("mfc0 %0,$" __STRING(reg) : "=r"(__val)); \ printf(" %s:%*s %#x\n", name, FLDWIDTH - (int) strlen(name), \ - "", __val); \ + "", (u_int)__val); \ } while (0) /* XXX not 64-bit ABI safe! */ @@ -341,8 +335,8 @@ uint64_t __val; \ \ __asm __volatile("dmfc0 %0,$" __STRING(reg):"=r"(__val)); \ - printf(" %s:%*s %#llx\n", name, FLDWIDTH - (int) strlen(name), \ - "", __val); \ + printf(" %s:%*s %#lx\n", name, FLDWIDTH - (int) strlen(name), \ + "", (u_long)__val); \ } while (0) DB_COMMAND(cp0, db_cp0dump_cmd) ==== //depot/projects/mips/sys/mips/mips/db_trace.c#4 (text+ko) ==== @@ -70,50 +70,51 @@ void db_mips_stack_trace(int, vm_offset_t, vm_offset_t, vm_offset_t, int, vm_offset_t); int db_mips_variable_func(const struct db_variable *, db_expr_t *, int); -#define DB_SETF_REGS db_mips_variable_func #define DBREGS_REG() struct db_variable db_regs[] = { - { "at", (long *)&ddb_regs.f_regs[AST], DB_SETF_REGS }, - { "v0", (long *)&ddb_regs.f_regs[V0], DB_SETF_REGS }, - { "v1", (long *)&ddb_regs.f_regs[V1], DB_SETF_REGS }, - { "a0", (long *)&ddb_regs.f_regs[A0], DB_SETF_REGS }, - { "a1", (long *)&ddb_regs.f_regs[A1], DB_SETF_REGS }, - { "a2", (long *)&ddb_regs.f_regs[A2], DB_SETF_REGS }, - { "a3", (long *)&ddb_regs.f_regs[A3], DB_SETF_REGS }, - { "a4", (long *)&ddb_regs.f_regs[A4], DB_SETF_REGS }, - { "a5", (long *)&ddb_regs.f_regs[A5], DB_SETF_REGS }, - { "a6", (long *)&ddb_regs.f_regs[A6], DB_SETF_REGS }, - { "a7", (long *)&ddb_regs.f_regs[A7], DB_SETF_REGS }, - { "t0", (long *)&ddb_regs.f_regs[T0], DB_SETF_REGS }, - { "t1", (long *)&ddb_regs.f_regs[T1], DB_SETF_REGS }, - { "t2", (long *)&ddb_regs.f_regs[T2], DB_SETF_REGS }, - { "t3", (long *)&ddb_regs.f_regs[T3], DB_SETF_REGS }, - { "s0", (long *)&ddb_regs.f_regs[S0], DB_SETF_REGS }, - { "s1", (long *)&ddb_regs.f_regs[S1], DB_SETF_REGS }, - { "s2", (long *)&ddb_regs.f_regs[S2], DB_SETF_REGS }, - { "s3", (long *)&ddb_regs.f_regs[S3], DB_SETF_REGS }, - { "s4", (long *)&ddb_regs.f_regs[S4], DB_SETF_REGS }, - { "s5", (long *)&ddb_regs.f_regs[S5], DB_SETF_REGS }, - { "s6", (long *)&ddb_regs.f_regs[S6], DB_SETF_REGS }, - { "s7", (long *)&ddb_regs.f_regs[S7], DB_SETF_REGS }, - { "t8", (long *)&ddb_regs.f_regs[T8], DB_SETF_REGS }, - { "t9", (long *)&ddb_regs.f_regs[T9], DB_SETF_REGS }, - { "k0", (long *)&ddb_regs.f_regs[K0], DB_SETF_REGS }, - { "k1", (long *)&ddb_regs.f_regs[K1], DB_SETF_REGS }, - { "gp", (long *)&ddb_regs.f_regs[GP], DB_SETF_REGS }, - { "sp", (long *)&ddb_regs.f_regs[SP], DB_SETF_REGS }, - { "fp", (long *)&ddb_regs.f_regs[S8], DB_SETF_REGS }, /* frame ptr */ - { "ra", (long *)&ddb_regs.f_regs[RA], DB_SETF_REGS }, - { "sr", (long *)&ddb_regs.f_regs[SR], DB_SETF_REGS }, - { "mdlo",(long *)&ddb_regs.f_regs[MULLO], DB_SETF_REGS }, - { "mdhi",(long *)&ddb_regs.f_regs[MULHI], DB_SETF_REGS }, - { "bad", (long *)&ddb_regs.f_regs[BADVADDR], DB_SETF_REGS }, - { "cs", (long *)&ddb_regs.f_regs[CAUSE], DB_SETF_REGS }, - { "pc", (long *)&ddb_regs.f_regs[PC], DB_SETF_REGS }, + { "at", (db_expr_t *)&ddb_regs.f_regs[AST], FCN_NULL }, + { "v0", (db_expr_t *)&ddb_regs.f_regs[V0], FCN_NULL }, + { "v1", (db_expr_t *)&ddb_regs.f_regs[V1], FCN_NULL }, + { "a0", (db_expr_t *)&ddb_regs.f_regs[A0], FCN_NULL }, + { "a1", (db_expr_t *)&ddb_regs.f_regs[A1], FCN_NULL }, + { "a2", (db_expr_t *)&ddb_regs.f_regs[A2], FCN_NULL }, + { "a3", (db_expr_t *)&ddb_regs.f_regs[A3], FCN_NULL }, + { "a4", (db_expr_t *)&ddb_regs.f_regs[A4], FCN_NULL }, + { "a5", (db_expr_t *)&ddb_regs.f_regs[A5], FCN_NULL }, + { "a6", (db_expr_t *)&ddb_regs.f_regs[A6], FCN_NULL }, + { "a7", (db_expr_t *)&ddb_regs.f_regs[A7], FCN_NULL }, + { "t0", (db_expr_t *)&ddb_regs.f_regs[T0], FCN_NULL }, + { "t1", (db_expr_t *)&ddb_regs.f_regs[T1], FCN_NULL }, + { "t2", (db_expr_t *)&ddb_regs.f_regs[T2], FCN_NULL }, + { "t3", (db_expr_t *)&ddb_regs.f_regs[T3], FCN_NULL }, + { "s0", (db_expr_t *)&ddb_regs.f_regs[S0], FCN_NULL }, + { "s1", (db_expr_t *)&ddb_regs.f_regs[S1], FCN_NULL }, + { "s2", (db_expr_t *)&ddb_regs.f_regs[S2], FCN_NULL }, + { "s3", (db_expr_t *)&ddb_regs.f_regs[S3], FCN_NULL }, + { "s4", (db_expr_t *)&ddb_regs.f_regs[S4], FCN_NULL }, + { "s5", (db_expr_t *)&ddb_regs.f_regs[S5], FCN_NULL }, + { "s6", (db_expr_t *)&ddb_regs.f_regs[S6], FCN_NULL }, + { "s7", (db_expr_t *)&ddb_regs.f_regs[S7], FCN_NULL }, + { "t8", (db_expr_t *)&ddb_regs.f_regs[T8], FCN_NULL }, + { "t9", (db_expr_t *)&ddb_regs.f_regs[T9], FCN_NULL }, + { "k0", (db_expr_t *)&ddb_regs.f_regs[K0], FCN_NULL }, + { "k1", (db_expr_t *)&ddb_regs.f_regs[K1], FCN_NULL }, + { "gp", (db_expr_t *)&ddb_regs.f_regs[GP], FCN_NULL }, + { "sp", (db_expr_t *)&ddb_regs.f_regs[SP], FCN_NULL }, + { "fp", (db_expr_t *)&ddb_regs.f_regs[S8], FCN_NULL }, /* frame ptr */ + { "ra", (db_expr_t *)&ddb_regs.f_regs[RA], FCN_NULL }, + { "sr", (db_expr_t *)&ddb_regs.f_regs[SR], FCN_NULL }, + { "mdlo",(db_expr_t *)&ddb_regs.f_regs[MULLO], FCN_NULL }, + { "mdhi",(db_expr_t *)&ddb_regs.f_regs[MULHI], FCN_NULL }, + { "bad", (db_expr_t *)&ddb_regs.f_regs[BADVADDR], FCN_NULL }, + { "cs", (db_expr_t *)&ddb_regs.f_regs[CAUSE], FCN_NULL }, + { "pc", (db_expr_t *)&ddb_regs.f_regs[PC], FCN_NULL }, }; struct db_variable *db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]); +extern char btext[]; + void db_stack_trace_cmd(db_expr_t addr, boolean_t have_addr, db_expr_t count, char *modif) @@ -129,8 +130,7 @@ InstFmt i; int stacksize; db_addr_t offset; - char *name; - extern char btext[]; + const char *name; pc = ddb_regs.f_regs[PC]; sp = ddb_regs.f_regs[SP]; @@ -166,8 +166,8 @@ db_find_sym_and_offset(func, &name, &offset); if (name == 0) name = "?"; - db_printf("%s()+0x%x, called by %p, stack size %d\n", - name, pc - func, (void *)ra, stacksize); + db_printf("%s()+0x%lx, called by %p, stack size %d\n", + name, (u_long)(pc - func), (void *)ra, stacksize); if (ra == pc) { db_printf("-- loop? --\n"); @@ -175,7 +175,7 @@ } sp += stacksize; pc = ra; - } while (pc > btext); + } while (pc > (register_t)btext); if (pc < 0x80000000) db_printf("-- user process --\n"); else @@ -191,22 +191,6 @@ } -int -db_mips_variable_func (const struct db_variable *vp, db_expr_t *valuep, - int db_var_fcn) -{ - - switch (db_var_fcn) { - case DB_VAR_GET: - *valuep = *(register_t *) vp->valuep; - break; - case DB_VAR_SET: - *(register_t *) vp->valuep = *valuep; - break; - } - return 0; -} - void db_print_backtrace(void) { ==== //depot/projects/mips/sys/mips/mips/locore_mips3.S#13 (text+ko) ==== @@ -89,8 +89,6 @@ #include "opt_ddb.h" -#include - #include #include #include ==== //depot/projects/mips/sys/mips/mips/machdep.c#34 (text+ko) ==== @@ -150,6 +150,8 @@ #include #include #include +#include +#include #include #include #include @@ -157,7 +159,9 @@ #include #include +#include #include +#include #include #include @@ -165,10 +169,15 @@ #include #include #include +#include #include #include #include +#ifdef DDB +#include +#endif + int cpu_arch; int mips_cpu_flags; int mips_has_r4k_mmu; @@ -192,11 +201,11 @@ vm_size_t physsz; +static void mips_vector_init(void); static void cpu_identify(void); void cpu_startup(void *); SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); - void mips_init(void) { @@ -572,19 +581,19 @@ memcpy((void *)addr, begin, len); } +/* r4000 exception handler address and end */ +extern char ExceptionVector[], ExceptionVectorEnd[]; + +/* TLB miss handler address and end */ +extern char TLBMissVector[], TLBMissVectorEnd[]; +extern char XTLBMissVector[], XTLBMissVectorEnd[]; + +/* Cache error handler */ +extern char CacheVector[], CacheVectorEnd[]; + static void mips64_vector_init(void) { - /* r4000 exception handler address and end */ - extern char ExceptionVector[], ExceptionVectorEnd[]; - - /* TLB miss handler address and end */ - extern char TLBMissVector[], TLBMissVectorEnd[]; - extern char XTLBMissVector[], XTLBMissVectorEnd[]; - - /* Cache error handler */ - extern char CacheVector[], CacheVectorEnd[]; - /* * Copy down exception vector code. */ @@ -628,7 +637,7 @@ * call locore cache and TLB management functions, based on the kind * of CPU the kernel is running on. */ -void +static void mips_vector_init(void) { const struct pridtab *ct; ==== //depot/projects/mips/sys/mips/mips/mips_subr.S#14 (text+ko) ==== @@ -121,8 +121,6 @@ */ #include "opt_ddb.h" -#include - #include #include #include ==== //depot/projects/mips/sys/mips/mips/pmap.c#18 (text+ko) ==== @@ -197,6 +197,9 @@ struct msgbuf *msgbufp; +PMAP_INLINE void pmap_kenter(vm_offset_t, vm_offset_t); +PMAP_INLINE void pmap_kremove(vm_offset_t); + /* * Data for the ASID allocator */ @@ -584,12 +587,13 @@ pmap_qenter(vm_offset_t sva, vm_page_t *m, int count) { vm_offset_t va; + int i; + i = 0; va = sva; while (count-- > 0) { - pmap_kenter(va, *m); + pmap_kenter(va, (vm_offset_t)m[i]); va += PAGE_SIZE; - m++; } } @@ -1786,57 +1790,6 @@ } /* - * pmap_emulate_reference: - * - * Emulate reference and/or modified bit hits. - * From NetBSD - */ -void -pmap_emulate_reference(struct vmspace *vm, vm_offset_t v, int user, int write) -{ - pt_entry_t faultoff, *pte; - vm_offset_t pa; - int user_addr; - - /* - * Convert process and virtual address to physical address. - */ - if (v >= VM_MIN_KERNEL_ADDRESS) { - if (user) - panic("pmap_emulate_reference: user ref to kernel"); - pte = pmap_pte(kernel_pmap, v); - user_addr = 0; - } else { - KASSERT(vm != NULL, ("pmap_emulate_reference: bad vmspace")); - pte = pmap_pte(vm->vm_map.pmap, v); - user_addr = 1; - } -#ifdef DEBUG /* These checks are more expensive */ - if (!pmap_pte_v(pte)) - panic("pmap_emulate_reference: invalid pte"); - /* Other diagnostics? */ -#endif - pa = pmap_pte_pa(pte); - - /* - * Twiddle the appropriate bits to reflect the reference - * and/or modification.. - * - * The rules: - * (1) always mark page as used, and - * (2) if it was a write fault, mark page as modified. - */ - if (write) { - faultoff = PG_D | PG_RO; - } else { - faultoff = PG_D; - } - - *pte = (*pte & ~faultoff); - MIPS_TBIS(v); -} - -/* * Miscellaneous support routines follow */ @@ -1850,17 +1803,13 @@ * uncached space. */ void * -pmap_mapdev(pa, size) - vm_offset_t pa; - vm_size_t size; +pmap_mapdev(vm_offset_t pa, vm_size_t size) { return (void*) MIPS_PHYS_TO_KSEG1(pa); } void -pmap_unmapdev(va, size) - vm_offset_t va; - vm_size_t size; +pmap_unmapdev(vm_offset_t va, vm_size_t size) { } @@ -1953,20 +1902,6 @@ } /* - * Deactivate the pmap for a thread. Go back to the kernel ASID. - */ -void -pmap_deactivate(struct thread *td) -{ - pmap_t pmap; - - pmap = vmspace_pmap(td->td_proc->p_vmspace); - atomic_clear_int(&pmap->pm_active, PCPU_GET(cpumask)); - pmap_active = 0; - mips_wr_entryhi(kernel_pmap->pm_asid); -} - -/* * XXX ? */ vm_offset_t ==== //depot/projects/mips/sys/mips/mips/syscall.c#2 (text+ko) ==== @@ -29,6 +29,9 @@ #include #include +/* XXX belongs in a header once things are actually meaningful. */ +void syscall_enter(void); + void syscall_enter(void) { ==== //depot/projects/mips/sys/mips/mips/tlb.c#5 (text+ko) ==== @@ -58,10 +58,12 @@ pt_entry_t *kptmap; vm_size_t kptsize; +#ifdef notyet /* * XXX Move the ASID code here. */ static int tlb_maxasid = MIPS3_TLB_NUM_ASIDS; +#endif void tlb_bootstrap(vm_size_t pages, vm_offset_t (*ptalloc)(vm_size_t)) @@ -134,7 +136,7 @@ tlb_remove_pages(pmap, va, eva - va); } -void +static void tlb_insert(vm_offset_t va, pt_entry_t pte0, pt_entry_t pte1) { va &= ~PAGE_MASK; ==== //depot/projects/mips/sys/mips/mips/trap.c#9 (text+ko) ==== @@ -31,9 +31,19 @@ #include #include +#include +#include + #include +#include +#include +#include #include +#ifdef DDB +#include +#endif + struct trap_identifier { u_int ExcCode; const char *Mnemonic; @@ -74,6 +84,9 @@ }; #define MAXTRAPID 31 +/* XXX belongs in a header some day? */ +void trap(struct trapframe *, u_int, void *); + void trap(struct trapframe *tf, u_int cause, void *badvaddr) { ==== //depot/projects/mips/sys/mips/sgimips/ip22.c#5 (text+ko) ==== @@ -68,7 +68,6 @@ unsigned long ip22_cal_timer(u_int32_t, u_int32_t); /* ip22_cache.S */ -extern void ip22_sdcache_do_wbinv(vaddr_t, vaddr_t); extern void ip22_sdcache_enable(void); extern void ip22_sdcache_disable(void); @@ -281,7 +280,9 @@ u_int32_t mstat; u_int32_t mmask; u_int32_t int23addr; - int which = (int)arg; + uintptr_t which; + + which = (uintptr_t)arg; if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) int23addr = 0x1fbd9000; ==== //depot/projects/mips/sys/mips/sgimips/machdep_sgimips.c#20 (text+ko) ==== @@ -37,6 +37,7 @@ #include #include #include +#include #include #include @@ -184,6 +185,7 @@ ctob(availmem) / (1024 * 1024)); } +#if notyet void cpu_intr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending) { @@ -192,6 +194,7 @@ else panic("Soft interrupt!?\n"); } +#endif /* * XXX Maybe return the state of the watchdog in enter, and pass it to