From owner-freebsd-mips@FreeBSD.ORG Fri Jul 15 10:08:10 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 85C53106566C for ; Fri, 15 Jul 2011 10:08:10 +0000 (UTC) (envelope-from adrian.chadd@gmail.com) Received: from mail-vx0-f182.google.com (mail-vx0-f182.google.com [209.85.220.182]) by mx1.freebsd.org (Postfix) with ESMTP id 40F378FC12 for ; Fri, 15 Jul 2011 10:08:09 +0000 (UTC) Received: by vxg33 with SMTP id 33so1085200vxg.13 for ; Fri, 15 Jul 2011 03:08:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=Ry6OViwCncid8greOwnQSUVSQOqU+a7+UcyH1/6qz/8=; b=QHTCvW0om/1uw90b9hGt2tG/xpySkDT+C5s3M5+ryj/9E5MkfuPS1ImL4JF1c2yk7z wGjeXcND1pRvpWHB/8+Qot1nxIN4nFhR4kvZbmxl70iffq3hTL1fZ4+qdNQXYqPmSBNX HqqP7SUY/ZxcepNRc96u6hhTTJwSBUjL+bUCQ= MIME-Version: 1.0 Received: by 10.52.97.8 with SMTP id dw8mr3694566vdb.150.1310724489388; Fri, 15 Jul 2011 03:08:09 -0700 (PDT) Sender: adrian.chadd@gmail.com Received: by 10.52.160.3 with HTTP; Fri, 15 Jul 2011 03:08:09 -0700 (PDT) In-Reply-To: References: Date: Fri, 15 Jul 2011 18:08:09 +0800 X-Google-Sender-Auth: d8fnI2BvokwFJfiIxAkSXTJSqOk Message-ID: From: Adrian Chadd To: Robert Millan Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Cc: freebsd-mips@freebsd.org Subject: Re: [PATCH] Fix initialization of i8259 controller on MALTA X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jul 2011 10:08:10 -0000 The obvious question - is QEMU correct here? Has anyone tried this on a real board? Adrian On 15 July 2011 08:16, Robert Millan wrote: > Hi, > > i8259 controller is initialized incorrectly on MALTA. =A0It writes mask > bits to control register and control bits to mask register. > > The former causes ICW1_RESET|ICW1_LTIM combination to be written to > control register, which on QEMU results in "level sensitive irq not > supported" error. > > -- > Robert Millan > > _______________________________________________ > freebsd-mips@freebsd.org mailing list > http://lists.freebsd.org/mailman/listinfo/freebsd-mips > To unsubscribe, send any mail to "freebsd-mips-unsubscribe@freebsd.org" > >