From owner-cvs-src@FreeBSD.ORG Sun Apr 6 14:32:44 2003 Return-Path: Delivered-To: cvs-src@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 9BC7437B401; Sun, 6 Apr 2003 14:32:44 -0700 (PDT) Received: from flood.ping.uio.no (flood.ping.uio.no [129.240.78.31]) by mx1.FreeBSD.org (Postfix) with ESMTP id 4808C43F93; Sun, 6 Apr 2003 14:32:43 -0700 (PDT) (envelope-from des@ofug.org) Received: by flood.ping.uio.no (Postfix, from userid 2602) id B8B325308; Sun, 6 Apr 2003 23:32:40 +0200 (CEST) X-URL: http://www.ofug.org/~des/ X-Disclaimer: The views expressed in this message do not necessarily coincide with those of any organisation or company with which I am or have been affiliated. To: Nate Lawson From: Dag-Erling Smorgrav Date: Sun, 06 Apr 2003 23:32:40 +0200 In-Reply-To: (Nate Lawson's message of "Sun, 6 Apr 2003 13:39:27 -0700 (PDT)") Message-ID: User-Agent: Gnus/5.090015 (Oort Gnus v0.15) Emacs/21.2 References: MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="=-=-=" cc: cvs-src@FreeBSD.org cc: src-committers@FreeBSD.org cc: cvs-all@FreeBSD.org cc: Tor.Egge@cvsup.no.freebsd.org Subject: Re: cvs commit: src/sys/conf options.i386 src/sys/i386/i386 tsc.c src/sys/i386/conf NOTES X-BeenThere: cvs-src@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 06 Apr 2003 21:32:45 -0000 --=-=-= Nate Lawson writes: > Perhaps you could enable this option by default if it had a corresponding > check for drift that would disable it if things got out of hand. There wouldn't be much point in that unless the SMP_TSC option also forced the TSC to be selected at boot time. On most SMP systems, the PIIX timecounter is automatically selected by virtue of being discovered last. On a related note, the attached patch converts the SMP_TSC option into a boot-time tunable. It also enables the TSC on single-CPU systems running an SMP kernel, since there is no synchronization problem with a single CPU. I must have bad benchmark karma, BTW - I can see no reduction of context switch time or any other significant performance boost when using the TSC on my dual Celeron system. DES -- Dag-Erling Smorgrav - des@ofug.org --=-=-= Content-Type: text/x-patch Content-Disposition: attachment; filename=smp_tsc.diff Index: conf/options.i386 =================================================================== RCS file: /home/ncvs/src/sys/conf/options.i386,v retrieving revision 1.189 diff -u -r1.189 options.i386 --- conf/options.i386 4 Apr 2003 23:54:46 -0000 1.189 +++ conf/options.i386 6 Apr 2003 21:16:49 -0000 @@ -41,7 +41,6 @@ CLK_CALIBRATION_LOOP opt_clock.h CLK_USE_I8254_CALIBRATION opt_clock.h CLK_USE_TSC_CALIBRATION opt_clock.h -SMP_TSC opt_clock.h TIMER_FREQ opt_clock.h NO_F00F_HACK opt_cpu.h Index: i386/conf/NOTES =================================================================== RCS file: /home/ncvs/src/sys/i386/conf/NOTES,v retrieving revision 1.1083 diff -u -r1.1083 NOTES --- i386/conf/NOTES 4 Apr 2003 23:54:46 -0000 1.1083 +++ i386/conf/NOTES 6 Apr 2003 21:18:01 -0000 @@ -247,11 +247,6 @@ options CLK_USE_I8254_CALIBRATION options CLK_USE_TSC_CALIBRATION -# One some SMP mainboards, the TSCs can be used in SMP mode due to -# them being synchronized. This can significantly reduce the context -# switch cost. -options SMP_TSC - ##################################################################### # MISCELLANEOUS DEVICES AND OPTIONS Index: i386/i386/tsc.c =================================================================== RCS file: /home/ncvs/src/sys/i386/i386/tsc.c,v retrieving revision 1.198 diff -u -r1.198 tsc.c --- i386/i386/tsc.c 4 Apr 2003 23:54:46 -0000 1.198 +++ i386/i386/tsc.c 6 Apr 2003 21:30:43 -0000 @@ -30,11 +30,12 @@ #include #include +#include #include #include #include -#include #include +#include #include #include #include @@ -43,6 +44,13 @@ int tsc_is_broken; u_int tsc_present; +#ifdef SMP +static int smp_tsc; +SYSCTL_INT(_kern_timecounter, OID_AUTO, smp_tsc, CTLFLAG_RD, &smp_tsc, 0, + "Indicates whether the TSC is safe to use in SMP mode"); +TUNABLE_INT("kern.timecounter.smp_tsc", &smp_tsc); +#endif + static unsigned tsc_get_timecount(struct timecounter *tc); static struct timecounter tsc_timecounter = { @@ -77,14 +85,17 @@ if (bootverbose) printf("TSC clock: %ju Hz\n", (intmax_t)tsc_freq); -#if defined(SMP) && !defined(SMP_TSC) +#ifdef SMP /* - * We can not use the TSC in SMP mode, until we figure out a - * cheap (impossible), reliable and precise (yeah right!) way - * to synchronize the TSCs of all the CPUs. - * Modern SMP hardware has the ACPI timer and we use that. + * We can not use the TSC in SMP mode unless the TSCs on all CPUs + * are somehow synchronized. Some hardware configurations do + * this, but we have no way of determining whether this is the + * case, so we do not use the TSC in multi-processor systems + * unless the user indicated (by setting kern.timecounter.smp_tsc + * to 1) that he believes that his TSCs are synchronized. */ - return; + if (mp_ncpus > 1 && !smp_tsc) + return; #endif /* Index: sys/timetc.h =================================================================== RCS file: /home/ncvs/src/sys/sys/timetc.h,v retrieving revision 1.56 diff -u -r1.56 timetc.h --- sys/timetc.h 29 Jan 2003 11:29:22 -0000 1.56 +++ sys/timetc.h 6 Apr 2003 21:23:57 -0000 @@ -64,4 +64,8 @@ void tc_setclock(struct timespec *ts); void tc_ticktock(void); +#ifdef SYSCTL_DECL +SYSCTL_DECL(_kern_timecounter); +#endif + #endif /* !_SYS_TIMETC_H_ */ --=-=-=--