From owner-svn-src-all@freebsd.org Tue Jun 20 11:11:43 2017 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id BC9C3D95BDB; Tue, 20 Jun 2017 11:11:43 +0000 (UTC) (envelope-from zbb@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 7C1DF7D826; Tue, 20 Jun 2017 11:11:43 +0000 (UTC) (envelope-from zbb@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v5KBBgHQ088704; Tue, 20 Jun 2017 11:11:42 GMT (envelope-from zbb@FreeBSD.org) Received: (from zbb@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v5KBBg3i088703; Tue, 20 Jun 2017 11:11:42 GMT (envelope-from zbb@FreeBSD.org) Message-Id: <201706201111.v5KBBg3i088703@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: zbb set sender to zbb@FreeBSD.org using -f From: Zbigniew Bodek Date: Tue, 20 Jun 2017 11:11:42 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r320142 - in head/sys/arm: arm include X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 20 Jun 2017 11:11:43 -0000 Author: zbb Date: Tue Jun 20 11:11:42 2017 New Revision: 320142 URL: https://svnweb.freebsd.org/changeset/base/320142 Log: Disable PL310 outer cache sync for IO coherent platforms When a PL310 cache is used on a system that provides hardware coherency, the outer cache sync operation is useless, and can be skipped. Moreover, on some systems, it is harmful as it causes deadlocks between the Marvell coherency mechanism, the Marvell PCIe or Crypto controllers and the Cortex-A9. To avoid this, this commit introduces a new Device Tree property 'arm,io-coherent' for the L2 cache controller node, valid only for the PL310 cache. It identifies the usage of the PL310 cache in an I/O coherent configuration. Internally, it makes the driver disable the outer cache sync operation. Note, that other outer-cache operations are not removed, as they may be needed for certain situations, such as booting secondary CPUs. Moreover, in order to enable IO coherent operation, the decision whether to use L2 cache maintenance callbacks is done in busdma layer, which was enabled in one of the previous commits. Submitted by: Michal Mazur Marcin Wojtas Reviewed by: mmel Obtained from: Semihalf Differential revision: https://reviews.freebsd.org/D11245 Modified: head/sys/arm/arm/pl310.c head/sys/arm/include/pl310.h Modified: head/sys/arm/arm/pl310.c ============================================================================== --- head/sys/arm/arm/pl310.c Tue Jun 20 11:09:38 2017 (r320141) +++ head/sys/arm/arm/pl310.c Tue Jun 20 11:11:42 2017 (r320142) @@ -206,6 +206,10 @@ pl310_cache_sync(void) if ((pl310_softc == NULL) || !pl310_softc->sc_enabled) return; + /* Do not sync outer cache on IO coherent platform */ + if (pl310_softc->sc_io_coherent) + return; + #ifdef PL310_ERRATA_753970 if (pl310_softc->sc_rtl_revision == CACHE_ID_RELEASE_r3p0) /* Write uncached PL310 register */ @@ -444,6 +448,7 @@ pl310_attach(device_t dev) struct pl310_softc *sc = device_get_softc(dev); int rid; uint32_t cache_id, debug_ctrl; + phandle_t node; sc->sc_dev = dev; rid = 0; @@ -469,6 +474,15 @@ pl310_attach(device_t dev) device_printf(dev, "Part number: 0x%x, release: 0x%x\n", (cache_id >> CACHE_ID_PARTNUM_SHIFT) & CACHE_ID_PARTNUM_MASK, (cache_id >> CACHE_ID_RELEASE_SHIFT) & CACHE_ID_RELEASE_MASK); + + /* + * Test for "arm,io-coherent" property and disable sync operation if + * platform is I/O coherent. Outer sync operations are not needed + * on coherent platform and may be harmful in certain situations. + */ + node = ofw_bus_get_node(dev); + if (OF_hasprop(node, "arm,io-coherent")) + sc->sc_io_coherent = true; /* * If L2 cache is already enabled then something has violated the rules, Modified: head/sys/arm/include/pl310.h ============================================================================== --- head/sys/arm/include/pl310.h Tue Jun 20 11:09:38 2017 (r320141) +++ head/sys/arm/include/pl310.h Tue Jun 20 11:11:42 2017 (r320142) @@ -148,6 +148,7 @@ struct pl310_softc { struct mtx sc_mtx; u_int sc_rtl_revision; struct intr_config_hook *sc_ich; + boolean_t sc_io_coherent; }; /**