Date: Sun, 2 Jul 2017 19:13:01 +0000 (UTC) From: Marius Strobl <marius@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r320577 - head/sys/dev/sdhci Message-ID: <201707021913.v62JD1fh060028@repo.freebsd.org>
next in thread | raw e-mail | index | archive | help
Author: marius Date: Sun Jul 2 19:13:01 2017 New Revision: 320577 URL: https://svnweb.freebsd.org/changeset/base/320577 Log: Retry up to 20 ms to enable bus power as at least with some Intel SDHCI/eMMC controllers the first attempt after a D3 to D0 transition, i. e. when the firmware has put the devices into D3 state before, can fail. Modified: head/sys/dev/sdhci/sdhci.c Modified: head/sys/dev/sdhci/sdhci.c ============================================================================== --- head/sys/dev/sdhci/sdhci.c Sun Jul 2 16:20:49 2017 (r320576) +++ head/sys/dev/sdhci/sdhci.c Sun Jul 2 19:13:01 2017 (r320577) @@ -366,6 +366,7 @@ sdhci_set_clock(struct sdhci_slot *slot, uint32_t cloc static void sdhci_set_power(struct sdhci_slot *slot, u_char power) { + int i; uint8_t pwr; if (slot->power == power) @@ -394,9 +395,20 @@ sdhci_set_power(struct sdhci_slot *slot, u_char power) break; } WR1(slot, SDHCI_POWER_CONTROL, pwr); - /* Turn on the power. */ + /* + * Turn on VDD1 power. Note that at least some Intel controllers can + * fail to enable bus power on the first try after transiting from D3 + * to D0, so we give them up to 20 ms. + */ pwr |= SDHCI_POWER_ON; - WR1(slot, SDHCI_POWER_CONTROL, pwr); + for (i = 0; i < 20; i++) { + WR1(slot, SDHCI_POWER_CONTROL, pwr); + if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON) + break; + DELAY(100); + } + if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)) + slot_printf(slot, "Bus power failed to enable"); if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10);
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201707021913.v62JD1fh060028>