Date: Tue, 14 May 1996 23:17:02 +0200 (MET DST) From: J Wunsch <j@uriah.heep.sax.de> To: davidg@Root.COM Cc: mmead@Glock.COM, joerg_wunsch@uriah.heep.sax.de, blh@nol.net, jgreco@brasil.moneng.mei.com, freebsd-chat@freebsd.org Subject: Re: Triton chipset with 256k cache caches 32M only? Message-ID: <199605142117.XAA01004@uriah.heep.sax.de> In-Reply-To: <199605141522.IAA12962@Root.COM> from David Greenman at "May 14, 96 08:22:48 am"
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As David Greenman wrote: > >> No, it uses the parity bits. Only 8 syndrome bits are needed > >> for 64bit words. > > > > Hmm. So does that mean the ECC is limited to single (odd > >number of) bit errors? > > ECC has single bit error correction and 2 bit error detection. Better than > parity no matter how you slice it. Btw., i'm now working with the new board. Well, uh, it's something like an improvement over the 3-year old 486/33 EISA board i've been using by now. (It's a 586/133 now, and of course, the memory is set to ECC.) -- cheers, J"org joerg_wunsch@uriah.heep.sax.de -- http://www.sax.de/~joerg/ -- NIC: JW11-RIPE Never trust an operating system you don't have sources for. ;-)
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