Date: Wed, 06 Jun 2018 14:59:44 +0000 From: bugzilla-noreply@freebsd.org To: ports-bugs@FreeBSD.org Subject: [Bug 227288] [New Port] cad/yosys: Framework for Verilog RTL synthesis Message-ID: <bug-227288-7788-VMAMMKyvtS@https.bugs.freebsd.org/bugzilla/> In-Reply-To: <bug-227288-7788@https.bugs.freebsd.org/bugzilla/> References: <bug-227288-7788@https.bugs.freebsd.org/bugzilla/>
next in thread | previous in thread | raw e-mail | index | archive | help
https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D227288 Tobias Kortkamp <tobik@freebsd.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Status|New |Closed Resolution|--- |Overcome By Events Assignee|ports-bugs@FreeBSD.org |tobik@freebsd.org --- Comment #1 from Tobias Kortkamp <tobik@freebsd.org> --- There were two submissions of yosys. I committed the other version in ports r471844. Sorry I didn't know this PR existed until now :-( --=20 You are receiving this mail because: You are the assignee for the bug.=
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?bug-227288-7788-VMAMMKyvtS>