Date: Thu, 28 Nov 2019 09:17:15 +0000 From: Andrew Turner <andrew@fubar.geek.nz> To: meloun.michal@gmail.com Cc: Alan Cox <alc@FreeBSD.org>, src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: Re: svn commit: r355145 - head/sys/arm64/arm64 Message-ID: <EBA9203E-17DF-455D-A491-EB4AEE0E37DF@fubar.geek.nz> In-Reply-To: <df22055b-2f80-2f9f-2b45-f66281435846@gmail.com> References: <201911272033.xARKXowX014908@repo.freebsd.org> <df22055b-2f80-2f9f-2b45-f66281435846@gmail.com>
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> On 28 Nov 2019, at 08:48, Michal Meloun <meloun.michal@gmail.com> = wrote: >=20 >=20 >=20 > On 27.11.2019 21:33, Alan Cox wrote: >> Author: alc >> Date: Wed Nov 27 20:33:49 2019 >> New Revision: 355145 >> URL: https://svnweb.freebsd.org/changeset/base/355145 >>=20 >> Log: >> There is no reason why we need to pin the underlying thread to its = current >> processor in pmap_invalidate_{all,page,range}(). These functions = are using >> an instruction that broadcasts the TLB invalidation to every = processor, so >> even if a thread migrates in the middle of one of these functions = every >> processor will still perform the required TLB invalidations. > I think this is not the right assumption. The problem is not in TLB > operations themselves, but in following 'dsb' and / or 'isb'. 'dsb' > ensures that all TLB operation transmitted by the local CPU is = performed > and visible to other observers. But it does nothing with TLBs emitted = by > other CPUs. > For example, if a given thread is rescheduled after all TLB operations > but before 'dsb' or 'isb' is performed, then the requested > synchronization does not occur at all. The tibi instructions need a context synchronisation point. One option = is the dsb & isb instructions, another is an exception entry. For a thread to be rescheduled it requires the timer interrupt to fire. = As an exception entry is a context synchronisation point and an = interrupt will cause an exception entry there will be such a point after = the the tibi instruction. Andrew
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