From owner-svn-src-head@freebsd.org Fri Oct 2 13:21:10 2015 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 6371CA0E006; Fri, 2 Oct 2015 13:21:10 +0000 (UTC) (envelope-from kib@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 54EFE1ECC; Fri, 2 Oct 2015 13:21:10 +0000 (UTC) (envelope-from kib@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.70]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id t92DLA1u002728; Fri, 2 Oct 2015 13:21:10 GMT (envelope-from kib@FreeBSD.org) Received: (from kib@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id t92DL9nr002723; Fri, 2 Oct 2015 13:21:09 GMT (envelope-from kib@FreeBSD.org) Message-Id: <201510021321.t92DL9nr002723@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: kib set sender to kib@FreeBSD.org using -f From: Konstantin Belousov Date: Fri, 2 Oct 2015 13:21:09 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r288491 - head/sys/arm/include X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Oct 2015 13:21:10 -0000 Author: kib Date: Fri Oct 2 13:21:08 2015 New Revision: 288491 URL: https://svnweb.freebsd.org/changeset/base/288491 Log: FreeBSD does not support SMP on ARMv5. Since processor is always self-consistent, there is no need in anything but compiler barrier in the implementation of atomic_thread_fence_*() on ARMv5. Split implementation of fences for ARMv4/5 and ARMv6; the former use compiler barriers, the later also perform hardware barriers. An issue which is fixed by the change is the faults from the CP15 coprocessor accesses in the user mode. This was uncovered by the pthread_once() changes in r287556. Reported by: Mattia Rossi Discussed with: alc, cognet, jhb Sponsored by: The FreeBSD Foundation MFC after: 1 week Modified: head/sys/arm/include/atomic-v4.h head/sys/arm/include/atomic-v6.h head/sys/arm/include/atomic.h Modified: head/sys/arm/include/atomic-v4.h ============================================================================== --- head/sys/arm/include/atomic-v4.h Fri Oct 2 13:16:06 2015 (r288490) +++ head/sys/arm/include/atomic-v4.h Fri Oct 2 13:21:08 2015 (r288491) @@ -439,4 +439,37 @@ atomic_subtract_long(volatile u_long *p, atomic_subtract_32((volatile uint32_t *)p, v); } +/* + * ARMv5 does not support SMP. For both kernel and user modes, only a + * compiler barrier is needed for fences, since CPU is always + * self-consistent. + */ +static __inline void +atomic_thread_fence_acq(void) +{ + + __compiler_membar(); +} + +static __inline void +atomic_thread_fence_rel(void) +{ + + __compiler_membar(); +} + +static __inline void +atomic_thread_fence_acq_rel(void) +{ + + __compiler_membar(); +} + +static __inline void +atomic_thread_fence_seq_cst(void) +{ + + __compiler_membar(); +} + #endif /* _MACHINE_ATOMIC_H_ */ Modified: head/sys/arm/include/atomic-v6.h ============================================================================== --- head/sys/arm/include/atomic-v6.h Fri Oct 2 13:16:06 2015 (r288490) +++ head/sys/arm/include/atomic-v6.h Fri Oct 2 13:21:08 2015 (r288491) @@ -596,4 +596,32 @@ atomic_store_rel_long(volatile u_long *p #undef ATOMIC_ACQ_REL #undef ATOMIC_ACQ_REL_LONG +static __inline void +atomic_thread_fence_acq(void) +{ + + dmb(); +} + +static __inline void +atomic_thread_fence_rel(void) +{ + + dmb(); +} + +static __inline void +atomic_thread_fence_acq_rel(void) +{ + + dmb(); +} + +static __inline void +atomic_thread_fence_seq_cst(void) +{ + + dmb(); +} + #endif /* _MACHINE_ATOMIC_V6_H_ */ Modified: head/sys/arm/include/atomic.h ============================================================================== --- head/sys/arm/include/atomic.h Fri Oct 2 13:16:06 2015 (r288490) +++ head/sys/arm/include/atomic.h Fri Oct 2 13:21:08 2015 (r288491) @@ -82,34 +82,6 @@ atomic_store_long(volatile u_long *dst, *dst = src; } -static __inline void -atomic_thread_fence_acq(void) -{ - - dmb(); -} - -static __inline void -atomic_thread_fence_rel(void) -{ - - dmb(); -} - -static __inline void -atomic_thread_fence_acq_rel(void) -{ - - dmb(); -} - -static __inline void -atomic_thread_fence_seq_cst(void) -{ - - dmb(); -} - #define atomic_clear_ptr atomic_clear_32 #define atomic_set_ptr atomic_set_32 #define atomic_cmpset_ptr atomic_cmpset_32