From owner-svn-src-head@freebsd.org Wed Sep 4 15:37:25 2019 Return-Path: Delivered-To: svn-src-head@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id A17EAF537A; Wed, 4 Sep 2019 15:37:25 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 46Nnxx4C6lz4SZd; Wed, 4 Sep 2019 15:37:25 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 73E6E1DB36; Wed, 4 Sep 2019 15:37:25 +0000 (UTC) (envelope-from br@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x84FbP7W083413; Wed, 4 Sep 2019 15:37:25 GMT (envelope-from br@FreeBSD.org) Received: (from br@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x84FbOJM083409; Wed, 4 Sep 2019 15:37:24 GMT (envelope-from br@FreeBSD.org) Message-Id: <201909041537.x84FbOJM083409@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: br set sender to br@FreeBSD.org using -f From: Ruslan Bukin Date: Wed, 4 Sep 2019 15:37:24 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r351817 - in head/sys: arm/altera/socfpga dev/gpio/dwgpio X-SVN-Group: head X-SVN-Commit-Author: br X-SVN-Commit-Paths: in head/sys: arm/altera/socfpga dev/gpio/dwgpio X-SVN-Commit-Revision: 351817 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Sep 2019 15:37:25 -0000 Author: br Date: Wed Sep 4 15:37:24 2019 New Revision: 351817 URL: https://svnweb.freebsd.org/changeset/base/351817 Log: o Add support for multi-port instances of Synopsys DesignWare APB GPIO Controller. o Rename the driver to dwgpio. Sponsored by: DARPA, AFRL Added: head/sys/dev/gpio/dwgpio/ head/sys/dev/gpio/dwgpio/dwgpio.c - copied, changed from r351816, head/sys/arm/altera/socfpga/socfpga_gpio.c head/sys/dev/gpio/dwgpio/dwgpio_bus.c (contents, props changed) head/sys/dev/gpio/dwgpio/dwgpio_if.m (contents, props changed) Deleted: head/sys/arm/altera/socfpga/socfpga_gpio.c Modified: head/sys/arm/altera/socfpga/files.socfpga Modified: head/sys/arm/altera/socfpga/files.socfpga ============================================================================== --- head/sys/arm/altera/socfpga/files.socfpga Wed Sep 4 14:32:04 2019 (r351816) +++ head/sys/arm/altera/socfpga/files.socfpga Wed Sep 4 15:37:24 2019 (r351817) @@ -5,7 +5,6 @@ arm/altera/socfpga/socfpga_machdep.c standard arm/altera/socfpga/socfpga_manager.c standard arm/altera/socfpga/socfpga_rstmgr.c standard arm/altera/socfpga/socfpga_mp.c optional smp -arm/altera/socfpga/socfpga_gpio.c optional gpio dev/mmc/host/dwmmc.c optional dwmmc dev/mmc/host/dwmmc_altera.c optional dwmmc Copied and modified: head/sys/dev/gpio/dwgpio/dwgpio.c (from r351816, head/sys/arm/altera/socfpga/socfpga_gpio.c) ============================================================================== --- head/sys/arm/altera/socfpga/socfpga_gpio.c Wed Sep 4 14:32:04 2019 (r351816, copy source) +++ head/sys/dev/gpio/dwgpio/dwgpio.c Wed Sep 4 15:37:24 2019 (r351817) @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2015 Ruslan Bukin + * Copyright (c) 2015, 2019 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of @@ -29,15 +29,12 @@ */ /* - * SOCFPGA General-Purpose I/O Interface. + * Synopsys® DesignWare® APB General Purpose Programming I/O + * (DW_apb_gpio) peripheral. + * * Chapter 22, Cyclone V Device Handbook (CV-5V2 2014.07.22) */ -/* - * The GPIO modules are instances of the Synopsys® DesignWare® APB General - * Purpose Programming I/O (DW_apb_gpio) peripheral. - */ - #include __FBSDID("$FreeBSD$"); @@ -53,6 +50,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include @@ -64,14 +62,13 @@ __FBSDID("$FreeBSD$"); #include #include "gpio_if.h" +#include "dwgpio_if.h" -#define READ4(_sc, _reg) \ - bus_read_4((_sc)->res[0], _reg) -#define WRITE4(_sc, _reg, _val) \ - bus_write_4((_sc)->res[0], _reg, _val) +#define READ4(_sc, _reg) DWGPIO_READ((_sc)->parent, _reg) +#define WRITE4(_sc, _reg, _val) DWGPIO_WRITE((_sc)->parent, _reg, _val) -#define GPIO_SWPORTA_DR 0x00 /* Port A Data Register */ -#define GPIO_SWPORTA_DDR 0x04 /* Port A Data Direction Register */ +#define GPIO_SWPORT_DR(n) (0x00 + 0xc * (n)) /* Port n Data Register */ +#define GPIO_SWPORT_DDR(n) (0x04 + 0xc * (n)) /* Port n Data Direction */ #define GPIO_INTEN 0x30 /* Interrupt Enable Register */ #define GPIO_INTMASK 0x34 /* Interrupt Mask Register */ #define GPIO_INTTYPE_LEVEL 0x38 /* Interrupt Level Register */ @@ -80,7 +77,7 @@ __FBSDID("$FreeBSD$"); #define GPIO_RAW_INTSTATUS 0x44 /* Raw Interrupt Status Register */ #define GPIO_DEBOUNCE 0x48 /* Debounce Enable Register */ #define GPIO_PORTA_EOI 0x4C /* Clear Interrupt Register */ -#define GPIO_EXT_PORTA 0x50 /* External Port A Register */ +#define GPIO_EXT_PORT(n) (0x50 + 0x4 * (n)) /* External Port n */ #define GPIO_LS_SYNC 0x60 /* Synchronization Level Register */ #define GPIO_ID_CODE 0x64 /* ID Code Register */ #define GPIO_VER_ID_CODE 0x6C /* GPIO Version Register */ @@ -89,13 +86,6 @@ __FBSDID("$FreeBSD$"); #define ENCODED_ID_PWIDTH_S(n) (5 * n) /* Width of GPIO Port N Shift */ #define GPIO_CONFIG_REG1 0x74 /* Configuration Register 1 */ -enum port_no { - PORTA, - PORTB, - PORTC, - PORTD, -}; - #define NR_GPIO_MAX 32 /* Maximum pins per port */ #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) @@ -106,43 +96,35 @@ enum port_no { /* * GPIO interface */ -static device_t socfpga_gpio_get_bus(device_t); -static int socfpga_gpio_pin_max(device_t, int *); -static int socfpga_gpio_pin_getcaps(device_t, uint32_t, uint32_t *); -static int socfpga_gpio_pin_getname(device_t, uint32_t, char *); -static int socfpga_gpio_pin_getflags(device_t, uint32_t, uint32_t *); -static int socfpga_gpio_pin_setflags(device_t, uint32_t, uint32_t); -static int socfpga_gpio_pin_set(device_t, uint32_t, unsigned int); -static int socfpga_gpio_pin_get(device_t, uint32_t, unsigned int *); -static int socfpga_gpio_pin_toggle(device_t, uint32_t pin); +static device_t dwgpio_get_bus(device_t); +static int dwgpio_pin_max(device_t, int *); +static int dwgpio_pin_getcaps(device_t, uint32_t, uint32_t *); +static int dwgpio_pin_getname(device_t, uint32_t, char *); +static int dwgpio_pin_getflags(device_t, uint32_t, uint32_t *); +static int dwgpio_pin_setflags(device_t, uint32_t, uint32_t); +static int dwgpio_pin_set(device_t, uint32_t, unsigned int); +static int dwgpio_pin_get(device_t, uint32_t, unsigned int *); +static int dwgpio_pin_toggle(device_t, uint32_t pin); -struct socfpga_gpio_softc { - struct resource *res[1]; - bus_space_tag_t bst; - bus_space_handle_t bsh; - +struct dwgpio_softc { device_t dev; device_t busdev; + device_t parent; struct mtx sc_mtx; int gpio_npins; struct gpio_pin gpio_pins[NR_GPIO_MAX]; + phandle_t node; + int port; }; -struct socfpga_gpio_softc *gpio_sc; - -static struct resource_spec socfpga_gpio_spec[] = { - { SYS_RES_MEMORY, 0, RF_ACTIVE }, - { -1, 0 } -}; - static int -socfpga_gpio_probe(device_t dev) +dwgpio_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); - if (!ofw_bus_is_compatible(dev, "snps,dw-apb-gpio")) + if (!ofw_bus_is_compatible(dev, "snps,dw-apb-gpio-port")) return (ENXIO); device_set_desc(dev, "DesignWare General-Purpose I/O Interface"); @@ -150,41 +132,32 @@ socfpga_gpio_probe(device_t dev) } static int -socfpga_gpio_attach(device_t dev) +dwgpio_attach(device_t dev) { - struct socfpga_gpio_softc *sc; + struct dwgpio_softc *sc; int version; int nr_pins; int cfg2; int i; sc = device_get_softc(dev); + sc->parent = device_get_parent(dev); + sc->node = ofw_bus_get_node(dev); sc->dev = dev; mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); - if (bus_alloc_resources(dev, socfpga_gpio_spec, sc->res)) { - device_printf(dev, "could not allocate resources\n"); - mtx_destroy(&sc->sc_mtx); + if ((OF_getencprop(sc->node, "reg", &sc->port, sizeof(sc->port))) <= 0) return (ENXIO); - } - /* Memory interface */ - sc->bst = rman_get_bustag(sc->res[0]); - sc->bsh = rman_get_bushandle(sc->res[0]); + printf("port %d\n", sc->port); - gpio_sc = sc; - version = READ4(sc, GPIO_VER_ID_CODE); -#if 0 - device_printf(sc->dev, "Version = 0x%08x\n", version); -#endif + if (boothowto & RB_VERBOSE) + device_printf(sc->dev, "Version = 0x%08x\n", version); - /* - * Take number of pins from hardware. - * XXX: Assume we have GPIO port A only. - */ + /* Grab number of pins from hardware. */ cfg2 = READ4(sc, GPIO_CONFIG_REG2); - nr_pins = (cfg2 >> ENCODED_ID_PWIDTH_S(PORTA)) & \ + nr_pins = (cfg2 >> ENCODED_ID_PWIDTH_S(sc->port)) & \ ENCODED_ID_PWIDTH_M; sc->gpio_npins = nr_pins + 1; @@ -192,14 +165,13 @@ socfpga_gpio_attach(device_t dev) sc->gpio_pins[i].gp_pin = i; sc->gpio_pins[i].gp_caps = DEFAULT_CAPS; sc->gpio_pins[i].gp_flags = - (READ4(sc, GPIO_SWPORTA_DDR) & (1 << i)) ? + (READ4(sc, GPIO_SWPORT_DDR(sc->port)) & (1 << i)) ? GPIO_PIN_OUTPUT: GPIO_PIN_INPUT; snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, - "socfpga_gpio%d.%d", device_get_unit(dev), i); + "dwgpio%d.%d", device_get_unit(dev), i); } sc->busdev = gpiobus_attach_bus(dev); if (sc->busdev == NULL) { - bus_release_resources(dev, socfpga_gpio_spec, sc->res); mtx_destroy(&sc->sc_mtx); return (ENXIO); } @@ -208,9 +180,9 @@ socfpga_gpio_attach(device_t dev) } static device_t -socfpga_gpio_get_bus(device_t dev) +dwgpio_get_bus(device_t dev) { - struct socfpga_gpio_softc *sc; + struct dwgpio_softc *sc; sc = device_get_softc(dev); @@ -218,9 +190,9 @@ socfpga_gpio_get_bus(device_t dev) } static int -socfpga_gpio_pin_max(device_t dev, int *maxpin) +dwgpio_pin_max(device_t dev, int *maxpin) { - struct socfpga_gpio_softc *sc; + struct dwgpio_softc *sc; sc = device_get_softc(dev); @@ -230,9 +202,9 @@ socfpga_gpio_pin_max(device_t dev, int *maxpin) } static int -socfpga_gpio_pin_getname(device_t dev, uint32_t pin, char *name) +dwgpio_pin_getname(device_t dev, uint32_t pin, char *name) { - struct socfpga_gpio_softc *sc; + struct dwgpio_softc *sc; int i; sc = device_get_softc(dev); @@ -252,9 +224,9 @@ socfpga_gpio_pin_getname(device_t dev, uint32_t pin, c } static int -socfpga_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) +dwgpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) { - struct socfpga_gpio_softc *sc; + struct dwgpio_softc *sc; int i; sc = device_get_softc(dev); @@ -274,9 +246,9 @@ socfpga_gpio_pin_getcaps(device_t dev, uint32_t pin, u } static int -socfpga_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) +dwgpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) { - struct socfpga_gpio_softc *sc; + struct dwgpio_softc *sc; int i; sc = device_get_softc(dev); @@ -296,9 +268,9 @@ socfpga_gpio_pin_getflags(device_t dev, uint32_t pin, } static int -socfpga_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) +dwgpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) { - struct socfpga_gpio_softc *sc; + struct dwgpio_softc *sc; int i; sc = device_get_softc(dev); @@ -311,16 +283,16 @@ socfpga_gpio_pin_get(device_t dev, uint32_t pin, unsig return (EINVAL); GPIO_LOCK(sc); - *val = (READ4(sc, GPIO_EXT_PORTA) & (1 << i)) ? 1 : 0; + *val = (READ4(sc, GPIO_EXT_PORT(sc->port)) & (1 << i)) ? 1 : 0; GPIO_UNLOCK(sc); return (0); } static int -socfpga_gpio_pin_toggle(device_t dev, uint32_t pin) +dwgpio_pin_toggle(device_t dev, uint32_t pin) { - struct socfpga_gpio_softc *sc; + struct dwgpio_softc *sc; int reg; int i; @@ -334,12 +306,12 @@ socfpga_gpio_pin_toggle(device_t dev, uint32_t pin) return (EINVAL); GPIO_LOCK(sc); - reg = READ4(sc, GPIO_SWPORTA_DR); + reg = READ4(sc, GPIO_SWPORT_DR(sc->port)); if (reg & (1 << i)) reg &= ~(1 << i); else reg |= (1 << i); - WRITE4(sc, GPIO_SWPORTA_DR, reg); + WRITE4(sc, GPIO_SWPORT_DR(sc->port), reg); GPIO_UNLOCK(sc); return (0); @@ -347,7 +319,7 @@ socfpga_gpio_pin_toggle(device_t dev, uint32_t pin) static void -socfpga_gpio_pin_configure(struct socfpga_gpio_softc *sc, +dwgpio_pin_configure(struct dwgpio_softc *sc, struct gpio_pin *pin, unsigned int flags) { int reg; @@ -358,7 +330,7 @@ socfpga_gpio_pin_configure(struct socfpga_gpio_softc * * Manage input/output */ - reg = READ4(sc, GPIO_SWPORTA_DDR); + reg = READ4(sc, GPIO_SWPORT_DDR(sc->port)); if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT); if (flags & GPIO_PIN_OUTPUT) { @@ -370,15 +342,15 @@ socfpga_gpio_pin_configure(struct socfpga_gpio_softc * } } - WRITE4(sc, GPIO_SWPORTA_DDR, reg); + WRITE4(sc, GPIO_SWPORT_DDR(sc->port), reg); GPIO_UNLOCK(sc); } static int -socfpga_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) +dwgpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) { - struct socfpga_gpio_softc *sc; + struct dwgpio_softc *sc; int i; sc = device_get_softc(dev); @@ -390,15 +362,15 @@ socfpga_gpio_pin_setflags(device_t dev, uint32_t pin, if (i >= sc->gpio_npins) return (EINVAL); - socfpga_gpio_pin_configure(sc, &sc->gpio_pins[i], flags); + dwgpio_pin_configure(sc, &sc->gpio_pins[i], flags); return (0); } static int -socfpga_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) +dwgpio_pin_set(device_t dev, uint32_t pin, unsigned int value) { - struct socfpga_gpio_softc *sc; + struct dwgpio_softc *sc; int reg; int i; @@ -413,41 +385,41 @@ socfpga_gpio_pin_set(device_t dev, uint32_t pin, unsig return (EINVAL); GPIO_LOCK(sc); - reg = READ4(sc, GPIO_SWPORTA_DR); + reg = READ4(sc, GPIO_SWPORT_DR(sc->port)); if (value) reg |= (1 << i); else reg &= ~(1 << i); - WRITE4(sc, GPIO_SWPORTA_DR, reg); + WRITE4(sc, GPIO_SWPORT_DR(sc->port), reg); GPIO_UNLOCK(sc); return (0); } -static device_method_t socfpga_gpio_methods[] = { - DEVMETHOD(device_probe, socfpga_gpio_probe), - DEVMETHOD(device_attach, socfpga_gpio_attach), +static device_method_t dwgpio_methods[] = { + DEVMETHOD(device_probe, dwgpio_probe), + DEVMETHOD(device_attach, dwgpio_attach), /* GPIO protocol */ - DEVMETHOD(gpio_get_bus, socfpga_gpio_get_bus), - DEVMETHOD(gpio_pin_max, socfpga_gpio_pin_max), - DEVMETHOD(gpio_pin_getname, socfpga_gpio_pin_getname), - DEVMETHOD(gpio_pin_getcaps, socfpga_gpio_pin_getcaps), - DEVMETHOD(gpio_pin_getflags, socfpga_gpio_pin_getflags), - DEVMETHOD(gpio_pin_get, socfpga_gpio_pin_get), - DEVMETHOD(gpio_pin_toggle, socfpga_gpio_pin_toggle), - DEVMETHOD(gpio_pin_setflags, socfpga_gpio_pin_setflags), - DEVMETHOD(gpio_pin_set, socfpga_gpio_pin_set), + DEVMETHOD(gpio_get_bus, dwgpio_get_bus), + DEVMETHOD(gpio_pin_max, dwgpio_pin_max), + DEVMETHOD(gpio_pin_getname, dwgpio_pin_getname), + DEVMETHOD(gpio_pin_getcaps, dwgpio_pin_getcaps), + DEVMETHOD(gpio_pin_getflags, dwgpio_pin_getflags), + DEVMETHOD(gpio_pin_get, dwgpio_pin_get), + DEVMETHOD(gpio_pin_toggle, dwgpio_pin_toggle), + DEVMETHOD(gpio_pin_setflags, dwgpio_pin_setflags), + DEVMETHOD(gpio_pin_set, dwgpio_pin_set), { 0, 0 } }; -static driver_t socfpga_gpio_driver = { +static driver_t dwgpio_driver = { "gpio", - socfpga_gpio_methods, - sizeof(struct socfpga_gpio_softc), + dwgpio_methods, + sizeof(struct dwgpio_softc), }; -static devclass_t socfpga_gpio_devclass; +static devclass_t dwgpio_devclass; -DRIVER_MODULE(socfpga_gpio, simplebus, socfpga_gpio_driver, - socfpga_gpio_devclass, 0, 0); +DRIVER_MODULE(dwgpio, dwgpiobus, dwgpio_driver, + dwgpio_devclass, 0, 0); Added: head/sys/dev/gpio/dwgpio/dwgpio_bus.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/dev/gpio/dwgpio/dwgpio_bus.c Wed Sep 4 15:37:24 2019 (r351817) @@ -0,0 +1,166 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Ruslan Bukin + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory (Department of Computer Science and + * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the + * DARPA SSITH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include "dwgpio_if.h" + +struct dwgpiobus_softc { + struct simplebus_softc simplebus_sc; + device_t dev; + struct resource *res[1]; +}; + +static struct resource_spec dwgpio_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { -1, 0 } +}; + +static int +dwgpiobus_probe(device_t dev) +{ + + if (!ofw_bus_is_compatible(dev, "snps,dw-apb-gpio")) + return (ENXIO); + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + device_set_desc(dev, "Synopsys® DesignWare® APB GPIO BUS"); + + return (BUS_PROBE_DEFAULT); +} + +static int +dwgpiobus_attach(device_t dev) +{ + struct dwgpiobus_softc *sc; + phandle_t node; + + sc = device_get_softc(dev); + sc->dev = dev; + + node = ofw_bus_get_node(dev); + if (node == -1) + return (ENXIO); + + if (bus_alloc_resources(dev, dwgpio_spec, sc->res)) { + device_printf(dev, "Could not allocate resources.\n"); + return (ENXIO); + } + + simplebus_init(dev, node); + + /* + * Allow devices to identify. + */ + bus_generic_probe(dev); + + /* + * Now walk the OFW tree and attach top-level devices. + */ + for (node = OF_child(node); node > 0; node = OF_peer(node)) + simplebus_add_device(dev, node, 0, NULL, -1, NULL); + + return (bus_generic_attach(dev)); +} + +static int +dwgpiobus_detach(device_t dev) +{ + struct dwgpiobus_softc *sc; + + sc = device_get_softc(dev); + + bus_release_resources(dev, dwgpio_spec, sc->res); + + return (0); +} + +static int +dwgpiobus_write(device_t dev, bus_size_t offset, int val) +{ + struct dwgpiobus_softc *sc; + + sc = device_get_softc(dev); + + bus_write_4(sc->res[0], offset, val); + + return (0); +}; + +static int +dwgpiobus_read(device_t dev, bus_size_t offset) +{ + struct dwgpiobus_softc *sc; + int val; + + sc = device_get_softc(dev); + + val = bus_read_4(sc->res[0], offset); + + return (val); +}; + +static device_method_t dwgpiobus_methods[] = { + DEVMETHOD(device_probe, dwgpiobus_probe), + DEVMETHOD(device_attach, dwgpiobus_attach), + DEVMETHOD(device_detach, dwgpiobus_detach), + + DEVMETHOD(dwgpio_write, dwgpiobus_write), + DEVMETHOD(dwgpio_read, dwgpiobus_read), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(dwgpiobus, dwgpiobus_driver, dwgpiobus_methods, + sizeof(struct dwgpiobus_softc), simplebus_driver); + +static devclass_t dwgpiobus_devclass; + +EARLY_DRIVER_MODULE(dwgpiobus, simplebus, dwgpiobus_driver, dwgpiobus_devclass, + 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); +MODULE_VERSION(dwgpiobus, 1); Added: head/sys/dev/gpio/dwgpio/dwgpio_if.m ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/dev/gpio/dwgpio/dwgpio_if.m Wed Sep 4 15:37:24 2019 (r351817) @@ -0,0 +1,52 @@ +#- +# Copyright (c) 2019 Ruslan Bukin +# +# This software was developed by SRI International and the University of +# Cambridge Computer Laboratory (Department of Computer Science and +# Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the +# DARPA SSITH research programme. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +# SUCH DAMAGE. +# +# $FreeBSD$ +# + +#include + +INTERFACE dwgpio; + +# +# GPIO write +# +METHOD int write { + device_t dev; + bus_size_t offset; + int val; +}; + +# +# GPIO read +# +METHOD int read { + device_t dev; + bus_size_t offset; +};