Date: Wed, 17 Dec 2008 15:54:25 +0000 (UTC) From: Rafal Jaworowski <raj@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r186230 - head/sys/powerpc/booke Message-ID: <200812171554.mBHFsPUB008056@svn.freebsd.org>
next in thread | raw e-mail | index | archive | help
Author: raj Date: Wed Dec 17 15:54:25 2008 New Revision: 186230 URL: http://svn.freebsd.org/changeset/base/186230 Log: Fix E500 cache invalidation routines. When invalidating the i/d-cache we need to wait until the core complex is really finished with the operation. Obtained from: Semihalf Modified: head/sys/powerpc/booke/locore.S Modified: head/sys/powerpc/booke/locore.S ============================================================================== --- head/sys/powerpc/booke/locore.S Wed Dec 17 15:44:34 2008 (r186229) +++ head/sys/powerpc/booke/locore.S Wed Dec 17 15:54:25 2008 (r186230) @@ -411,6 +411,9 @@ ENTRY(dcache_inval) isync mtspr SPR_L1CSR0, %r3 isync +1: mfspr %r3, SPR_L1CSR0 + andi. %r3, %r3, L1CSR0_DCFI + bne 1b blr ENTRY(dcache_disable) @@ -443,6 +446,9 @@ ENTRY(icache_inval) isync mtspr SPR_L1CSR1, %r3 isync +1: mfspr %r3, SPR_L1CSR1 + andi. %r3, %r3, L1CSR1_ICFI + bne 1b blr ENTRY(icache_disable)
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?200812171554.mBHFsPUB008056>