From nobody Wed Apr 2 16:57:10 2025 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4ZSWHp6y0pz5sXFs; Wed, 02 Apr 2025 16:57:10 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R10" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4ZSWHp4bGyz3wPk; Wed, 02 Apr 2025 16:57:10 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1743613030; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=BmdhR1iJcQ2LlYWyWAgO/nxRGZhmK8SAWlfvpeJjTdk=; b=JIS3MaCd9lrFFqgY3IXQhu2mIxV0zq0oiAfaNlkP3arf/GGQ6vZ+HeTp0pBnR8wvzS6IbS a8Jg6WQNX5dr0Pr6/p9+Gs3bQDc3fcs4SBKrfiJQCjwSydR0Cn1qb4uU60LNRfjYaE15vD 1upfZJOPFWHKyK0RfPIBEiv+kuOHLJB1j7DDWbgJgLfGq7gxwtK5IKRZnD6PIl3OptcGip Z5RN1DMBcCn563+Xc8Zb7c22DtJxwYSa6nExG5JbTeEITFJMvtZ2TMwOzIiZjyZDognMiD diR7nVbYoBi2r+9tYJnWgLOoovM27cpxRV2wdfWOyKJgmVqLXHsZA9wgSeOB+Q== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1743613030; a=rsa-sha256; cv=none; b=dGZ1og2RSOAo4tK0v6U03NJpiYV3Fpsb2URPGdR0A9M8xJo5t9uPvFKLosi4FisocNhEm6 Qh4QLAEI8R2QUKm5G6jdu+pXeDGgheGpSWszJ2M6z91I47hbadK3My7j3gTES5vugZJrBD 3j7ayiea1UNaNNSd1K4fnOu6PnvH3wbRjOL6JU+kbukqgs3jhxz488AMAxQcVQOOHkleOr rQxmx6HqVcwowpcJ5qdoAIkKW5lwodBVWrAgEJC8kznqylISBJqjGNMijDnjD08rY5aiWk 8QcZWFE5FW1mkPMO640zRgVJxKThhaxehm0PMvpvYee37tHNkr9jY2bbnMnghQ== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1743613030; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=BmdhR1iJcQ2LlYWyWAgO/nxRGZhmK8SAWlfvpeJjTdk=; b=jiYLSUtpi/K5ZPnSI+fqx8C8Lip2oP33YpUEbf8AVZO6fXv7LsswWSpnZ6rrAtnrdTAVzn RHDfq7lIt67Hy7gsCSvNpfbHXhZXYmuKu6PdquRP0z9jSkxo0KVxx0WVmzAgtA3bR/LJPY OzubaVtE5gf1XVw7bjql1/+UL47M4NBjQyAx4VlOY/YD+UHa/YsXecJZOR6VurEzhb6msA knpAD4YxjMKyKnDm77oZQ7OoNhwTdBiPAx+cHZmZ6agGbof3rgtxfHToIj2tjgqxI+R0m2 4SHNpKrxjoRhsEHczQoMhm9VGAsfUC9GXdjVDe6H4hRFwFoWjPtkDCfXKgV8Jg== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4ZSWHp47hCz8TC; Wed, 02 Apr 2025 16:57:10 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.18.1/8.18.1) with ESMTP id 532GvAtY049215; Wed, 2 Apr 2025 16:57:10 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.18.1/8.18.1/Submit) id 532GvAcA049212; Wed, 2 Apr 2025 16:57:10 GMT (envelope-from git) Date: Wed, 2 Apr 2025 16:57:10 GMT Message-Id: <202504021657.532GvAcA049212@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Mitchell Horne Subject: git: cd92dd23241e - main - eqos: Add StarFive JH7110 variant List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mhorne X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: cd92dd23241e22dce06ebeb0c8e98eec5afcc896 Auto-Submitted: auto-generated The branch main has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=cd92dd23241e22dce06ebeb0c8e98eec5afcc896 commit cd92dd23241e22dce06ebeb0c8e98eec5afcc896 Author: Jari Sihvola AuthorDate: 2025-04-02 16:30:23 +0000 Commit: Mitchell Horne CommitDate: 2025-04-02 16:56:38 +0000 eqos: Add StarFive JH7110 variant Found on the VisionFive v2 SBC, and similar. Reviewed by: mhorne Tested by: mhorne Discussed with: sos Differential Revision: https://reviews.freebsd.org/D45600 --- sys/dev/eqos/if_eqos.c | 33 ++++-- sys/dev/eqos/if_eqos_reg.h | 1 + sys/dev/eqos/if_eqos_starfive.c | 219 ++++++++++++++++++++++++++++++++++++++ sys/dev/eqos/if_eqos_var.h | 7 ++ sys/riscv/conf/std.starfive | 2 + sys/riscv/starfive/files.starfive | 4 + 6 files changed, 260 insertions(+), 6 deletions(-) diff --git a/sys/dev/eqos/if_eqos.c b/sys/dev/eqos/if_eqos.c index 6e2eea2e6c37..de3d8da7c3bf 100644 --- a/sys/dev/eqos/if_eqos.c +++ b/sys/dev/eqos/if_eqos.c @@ -456,7 +456,7 @@ eqos_reset(struct eqos_softc *sc) int retry; WR4(sc, GMAC_DMA_MODE, GMAC_DMA_MODE_SWR); - for (retry = 2000; retry > 0; retry--) { + for (retry = 5000; retry > 0; retry--) { DELAY(1000); val = RD4(sc, GMAC_DMA_MODE); if (!(val & GMAC_DMA_MODE_SWR)) @@ -491,7 +491,7 @@ eqos_init(void *if_softc) struct eqos_softc *sc = if_softc; if_t ifp = sc->ifp; struct mii_data *mii = device_get_softc(sc->miibus); - uint32_t val; + uint32_t val, mtl_tx_val, mtl_rx_val; if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) return; @@ -508,13 +508,18 @@ eqos_init(void *if_softc) val = RD4(sc, GMAC_DMA_CHAN0_CONTROL); val &= ~GMAC_DMA_CHAN0_CONTROL_DSL_MASK; val |= ((DESC_ALIGN - 16) / 8) << GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT; - val |= GMAC_DMA_CHAN0_CONTROL_PBLX8; + if (sc->pblx8) + val |= GMAC_DMA_CHAN0_CONTROL_PBLX8; WR4(sc, GMAC_DMA_CHAN0_CONTROL, val); val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL); + if (sc->txpbl > 0) + val |= (sc->txpbl << GMAC_DMA_CHAN0_TXRX_PBL_SHIFT); val |= GMAC_DMA_CHAN0_TX_CONTROL_OSP; val |= GMAC_DMA_CHAN0_TX_CONTROL_START; WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val); val = RD4(sc, GMAC_DMA_CHAN0_RX_CONTROL); + if (sc->rxpbl > 0) + val |= (sc->rxpbl << GMAC_DMA_CHAN0_TXRX_PBL_SHIFT); val &= ~GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_MASK; val |= (MCLBYTES << GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT); val |= GMAC_DMA_CHAN0_RX_CONTROL_START; @@ -527,11 +532,19 @@ eqos_init(void *if_softc) GMAC_MMC_CONTROL_CNTPRSTLVL); /* Configure operation modes */ + if (sc->thresh_dma_mode) { + mtl_tx_val = sc->ttc; + mtl_rx_val = sc->rtc; + } else { + mtl_tx_val = GMAC_MTL_TXQ0_OPERATION_MODE_TSF; + mtl_rx_val = GMAC_MTL_RXQ0_OPERATION_MODE_RSF; + } + WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, - GMAC_MTL_TXQ0_OPERATION_MODE_TSF | + mtl_tx_val | GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_EN); WR4(sc, GMAC_MTL_RXQ0_OPERATION_MODE, - GMAC_MTL_RXQ0_OPERATION_MODE_RSF | + mtl_rx_val | GMAC_MTL_RXQ0_OPERATION_MODE_FEP | GMAC_MTL_RXQ0_OPERATION_MODE_FUP); @@ -1112,6 +1125,14 @@ eqos_attach(device_t dev) int error; int n; + /* default values */ + sc->thresh_dma_mode = false; + sc->pblx8 = true; + sc->txpbl = 0; + sc->rxpbl = 0; + sc->ttc = 0x10; + sc->rtc = 0; + /* setup resources */ if (bus_alloc_resources(dev, eqos_spec, sc->res)) { device_printf(dev, "Could not allocate resources\n"); @@ -1128,7 +1149,7 @@ eqos_attach(device_t dev) GMAC_MAC_VERSION_USERVER_SHIFT; snpsver = ver & GMAC_MAC_VERSION_SNPSVER_MASK; - if (snpsver != 0x51) { + if (snpsver != 0x51 && snpsver != 0x52) { device_printf(dev, "EQOS version 0x%02x not supported\n", snpsver); return (ENXIO); diff --git a/sys/dev/eqos/if_eqos_reg.h b/sys/dev/eqos/if_eqos_reg.h index f9e7f9368cf2..fe7440bd19c7 100644 --- a/sys/dev/eqos/if_eqos_reg.h +++ b/sys/dev/eqos/if_eqos_reg.h @@ -241,6 +241,7 @@ #define GMAC_DMA_CHAN0_RX_END_ADDR 0x1128 #define GMAC_DMA_CHAN0_TX_RING_LEN 0x112C #define GMAC_DMA_CHAN0_RX_RING_LEN 0x1130 +#define GMAC_DMA_CHAN0_TXRX_PBL_SHIFT 16 #define GMAC_DMA_CHAN0_INTR_ENABLE 0x1134 #define GMAC_DMA_CHAN0_INTR_ENABLE_NIE (1U << 15) #define GMAC_DMA_CHAN0_INTR_ENABLE_AIE (1U << 14) diff --git a/sys/dev/eqos/if_eqos_starfive.c b/sys/dev/eqos/if_eqos_starfive.c new file mode 100644 index 000000000000..62f8b3f38983 --- /dev/null +++ b/sys/dev/eqos/if_eqos_starfive.c @@ -0,0 +1,219 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2024 Jari Sihvola + */ + +#include "opt_platform.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include + +#include "if_eqos_if.h" +#include "gpio_if.h" + +#include + +/* JH7110's board specific code for eqos Ethernet controller driver */ + +#define JH7110_CSR_FREQ 198000000 + +#define WR4(sc, o, v) bus_write_4(sc->base.res[EQOS_RES_MEM], (o), (v)) + +static const struct ofw_compat_data compat_data[] = { + {"starfive,jh7110-dwmac", 1}, + { NULL, 0} +}; + +struct if_eqos_starfive_softc { + struct eqos_softc base; + clk_t gtx; + clk_t tx; + clk_t stmmaceth; + clk_t pclk; +}; + +static int +if_eqos_starfive_set_speed(device_t dev, int speed) +{ + struct if_eqos_starfive_softc *sc = device_get_softc(dev); + uint64_t freq; + int err; + + switch (speed) { + case IFM_1000_T: + case IFM_1000_SX: + freq = 125000000; + break; + case IFM_100_TX: + freq = 25000000; + break; + case IFM_10_T: + freq = 2500000; + break; + default: + device_printf(dev, "unsupported media %u\n", speed); + return (-EINVAL); + } + + clk_set_freq(sc->gtx, freq, 0); + err = clk_enable(sc->gtx); + if (err != 0) { + device_printf(dev, "Could not enable clock %s\n", + clk_get_name(sc->gtx)); + } + + return (0); +} + + + +static int +if_eqos_starfive_clk_init(device_t dev) +{ + struct if_eqos_starfive_softc *sc = device_get_softc(dev); + int err; + + if (clk_get_by_ofw_name(dev, 0, "gtx", &sc->gtx) != 0) { + device_printf(sc->base.dev, "could not get gtx clock\n"); + return (ENXIO); + } + + if (clk_get_by_ofw_name(dev, 0, "tx", &sc->tx) == 0) { + err = clk_enable(sc->tx); + if (err != 0) { + device_printf(dev, "Could not enable clock %s\n", + clk_get_name(sc->tx)); + } + } + if (clk_get_by_ofw_name(dev, 0, "stmmaceth", &sc->stmmaceth) == 0) { + err = clk_enable(sc->stmmaceth); + if (err != 0) { + device_printf(dev, "Could not enable clock %s\n", + clk_get_name(sc->stmmaceth)); + } + } + if (clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk) == 0) { + err = clk_enable(sc->pclk); + if (err != 0) { + device_printf(dev, "Could not enable clock %s\n", + clk_get_name(sc->pclk)); + } + } + + return (0); +} + +static int +if_eqos_starfive_init(device_t dev) +{ + struct if_eqos_starfive_softc *sc = device_get_softc(dev); + hwreset_t rst_ahb, rst_stmmaceth; + phandle_t node; + + node = ofw_bus_get_node(dev); + + sc->base.ttc = 0x10; + sc->base.rtc = 0; + + if (OF_hasprop(node, "snps,force_thresh_dma_mode")) + sc->base.thresh_dma_mode = true; + + if (OF_hasprop(node, "snps,no-pbl-x8")) + sc->base.pblx8 = false; + + if (OF_hasprop(node, "snps,txpbl")) { + OF_getencprop(node, "snps,txpbl", &sc->base.txpbl, + sizeof(sc->base.txpbl)); + } + if (OF_hasprop(node, "snps,rxpbl")) { + OF_getencprop(node, "snps,rxpbl", &sc->base.rxpbl, + sizeof(sc->base.rxpbl)); + } + + if (hwreset_get_by_ofw_name(dev, 0, "ahb", &rst_ahb)) { + device_printf(dev, "Cannot get ahb reset\n"); + return (ENXIO); + } + if (hwreset_assert(rst_ahb) != 0) { + device_printf(dev, "Cannot assert ahb reset\n"); + return (ENXIO); + } + + if (hwreset_get_by_ofw_name(dev, 0, "stmmaceth", &rst_stmmaceth)) { + device_printf(dev, "Cannot get stmmaceth reset\n"); + return (ENXIO); + } + if (hwreset_assert(rst_stmmaceth) != 0) { + device_printf(dev, "Cannot assert stmmaceth reset\n"); + return (ENXIO); + } + + sc->base.csr_clock = JH7110_CSR_FREQ; + sc->base.csr_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_150_250; + + if (if_eqos_starfive_clk_init(dev) != 0) { + device_printf(dev, "Clock initialization failed\n"); + return (ENXIO); + } + if (hwreset_deassert(rst_ahb) != 0) { + device_printf(dev, "Cannot deassert rst_ahb\n"); + return (ENXIO); + } + if (hwreset_deassert(rst_stmmaceth) != 0) { + device_printf(dev, "Cannot deassert rst_stmmaceth\n"); + return (ENXIO); + } + + return (0); +} + +static int +eqos_starfive_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "DesignWare EQOS Gigabit Ethernet for JH7110"); + + return (BUS_PROBE_DEFAULT); +} + + +static device_method_t eqos_starfive_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, eqos_starfive_probe), + + /* EQOS interface */ + DEVMETHOD(if_eqos_init, if_eqos_starfive_init), + DEVMETHOD(if_eqos_set_speed, if_eqos_starfive_set_speed), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(eqos, eqos_starfive_driver, eqos_starfive_methods, + sizeof(struct if_eqos_starfive_softc), eqos_driver); +DRIVER_MODULE(eqos_starfive, simplebus, eqos_starfive_driver, 0, 0); diff --git a/sys/dev/eqos/if_eqos_var.h b/sys/dev/eqos/if_eqos_var.h index c21a703747ec..892b15ba589e 100644 --- a/sys/dev/eqos/if_eqos_var.h +++ b/sys/dev/eqos/if_eqos_var.h @@ -85,6 +85,13 @@ struct eqos_softc { bool link_up; int tx_watchdog; + bool thresh_dma_mode; + bool pblx8; + uint32_t txpbl; + uint32_t rxpbl; + uint32_t ttc; + uint32_t rtc; + struct ifnet *ifp; device_t miibus; struct mtx lock; diff --git a/sys/riscv/conf/std.starfive b/sys/riscv/conf/std.starfive index e4e3e7c46f3e..9bdb1af9e79c 100644 --- a/sys/riscv/conf/std.starfive +++ b/sys/riscv/conf/std.starfive @@ -4,6 +4,8 @@ device uart_snps # DesignWare Synopsis UART driver +device eqos + # MMC/SD/SDIO Card slot support device dwmmc device dwmmc_starfive diff --git a/sys/riscv/starfive/files.starfive b/sys/riscv/starfive/files.starfive index 10c56448970d..57d4618d00f9 100644 --- a/sys/riscv/starfive/files.starfive +++ b/sys/riscv/starfive/files.starfive @@ -5,4 +5,8 @@ dev/clk/starfive/jh7110_clk_sys.c standard dev/clk/starfive/jh7110_clk_stg.c standard dev/mmc/host/dwmmc_starfive.c optional dwmmc_starfive fdt +dev/eqos/if_eqos.c optional eqos +dev/eqos/if_eqos_if.m optional eqos +dev/eqos/if_eqos_starfive.c optional eqos + riscv/starfive/starfive_syscon.c standard