From owner-freebsd-arm@FreeBSD.ORG Wed Jul 8 10:40:58 2009 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id A70161065670; Wed, 8 Jul 2009 10:40:58 +0000 (UTC) (envelope-from sebastian.huber@embedded-brains.de) Received: from mail.embedded-brains.de (host-82-135-62-35.customer.m-online.net [82.135.62.35]) by mx1.freebsd.org (Postfix) with ESMTP id 54E6C8FC08; Wed, 8 Jul 2009 10:40:58 +0000 (UTC) (envelope-from sebastian.huber@embedded-brains.de) Received: by mail.embedded-brains.de (Postfix, from userid 65534) id 8B4066F8260; Wed, 8 Jul 2009 12:30:47 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.2.3 (2007-08-08) on fidibus X-Spam-Level: X-Spam-Status: No, score=-3.4 required=5.0 tests=ALL_TRUSTED,AWL,BAYES_00 autolearn=ham version=3.2.3 Received: from [192.168.96.31] (eb0011.eb.z [192.168.96.31]) by mail.embedded-brains.de (Postfix) with ESMTP id 5C83E6F825E; Wed, 8 Jul 2009 12:30:46 +0200 (CEST) Message-ID: <4A547556.4050801@embedded-brains.de> Date: Wed, 08 Jul 2009 12:30:46 +0200 From: Sebastian Huber User-Agent: Thunderbird 2.0.0.19 (X11/20081227) MIME-Version: 1.0 To: =?ISO-8859-2?Q?Piotr_Zi=EAcik?= References: <200906231035.43096.kosmo@semihalf.com> <37C51279-42D8-49DE-8249-0DA386EBB062@semihalf.com> <200907081103.45388.hselasky@c2i.net> <200907081216.40100.kosmo@semihalf.com> In-Reply-To: <200907081216.40100.kosmo@semihalf.com> Content-Type: text/plain; charset=ISO-8859-2 Content-Transfer-Encoding: 8bit Cc: freebsd-arm@freebsd.org, freebsd-usb@freebsd.org, thompsa@freebsd.org Subject: Re: CPU Cache and busdma usage in USB X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 08 Jul 2009 10:40:58 -0000 Hi! The general approach for systems with no hardware cache coherence protocol should be: Memory to device DMA transfer of a buffer: 1. write all modified cache lines of the buffer back to memory (cache flush for buffer) 2. start DMA transfer Device to memory DMA transfer of a buffer: 1. invalidate the cache of the buffer, here you have to make sure that this buffer does not share a cache line with other buffers (!) 2. start DMA transfer 3. all accesses to the buffer via the cache must wait until the DMA has finished CU -- Sebastian Huber, Embedded Brains GmbH Address : Obere Lagerstr. 30, D-82178 Puchheim, Germany Phone : +49 89 18 90 80 79-6 Fax : +49 89 18 90 80 79-9 E-Mail : sebastian.huber@embedded-brains.de PGP : Public key available on request Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.