From owner-svn-src-head@freebsd.org Wed Jun 26 16:56:57 2019 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 6088F15CCE66; Wed, 26 Jun 2019 16:56:57 +0000 (UTC) (envelope-from cognet@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 05F0375B3A; Wed, 26 Jun 2019 16:56:57 +0000 (UTC) (envelope-from cognet@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id CBDFA27AA; Wed, 26 Jun 2019 16:56:56 +0000 (UTC) (envelope-from cognet@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x5QGuuPI061821; Wed, 26 Jun 2019 16:56:56 GMT (envelope-from cognet@FreeBSD.org) Received: (from cognet@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x5QGuuwS061820; Wed, 26 Jun 2019 16:56:56 GMT (envelope-from cognet@FreeBSD.org) Message-Id: <201906261656.x5QGuuwS061820@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: cognet set sender to cognet@FreeBSD.org using -f From: Olivier Houchard Date: Wed, 26 Jun 2019 16:56:56 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r349426 - head/sys/arm64/arm64 X-SVN-Group: head X-SVN-Commit-Author: cognet X-SVN-Commit-Paths: head/sys/arm64/arm64 X-SVN-Commit-Revision: 349426 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 05F0375B3A X-Spamd-Bar: -- Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-2.96 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_MEDIUM(-1.00)[-0.999,0]; NEURAL_HAM_LONG(-1.00)[-1.000,0]; NEURAL_HAM_SHORT(-0.96)[-0.956,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 26 Jun 2019 16:56:57 -0000 Author: cognet Date: Wed Jun 26 16:56:56 2019 New Revision: 349426 URL: https://svnweb.freebsd.org/changeset/base/349426 Log: Fix debugging of 32bits arm binaries on arm64. In set_regs32()/fill_regs32(), we have to get/set SP and LR from/to tf_x[13] and tf_x[14]. set_regs() and fill_regs() may be called for a 32bits process, if the process is ptrace'd from a 64bits debugger. So, in set_regs() and fill_regs(), get or set PC and SPSR from where the debugger expects it, from tf_x[15] and tf_x[16]. Modified: head/sys/arm64/arm64/machdep.c Modified: head/sys/arm64/arm64/machdep.c ============================================================================== --- head/sys/arm64/arm64/machdep.c Wed Jun 26 16:38:46 2019 (r349425) +++ head/sys/arm64/arm64/machdep.c Wed Jun 26 16:56:56 2019 (r349426) @@ -194,6 +194,16 @@ fill_regs(struct thread *td, struct reg *regs) memcpy(regs->x, frame->tf_x, sizeof(regs->x)); +#ifdef COMPAT_FREEBSD32 + /* + * We may be called here for a 32bits process, if we're using a + * 64bits debugger. If so, put PC and SPSR where it expects it. + */ + if (SV_PROC_FLAG(td->td_proc, SV_ILP32)) { + regs->x[15] = frame->tf_elr; + regs->x[16] = frame->tf_spsr; + } +#endif return (0); } @@ -211,6 +221,17 @@ set_regs(struct thread *td, struct reg *regs) memcpy(frame->tf_x, regs->x, sizeof(frame->tf_x)); +#ifdef COMPAT_FREEBSD32 + if (SV_PROC_FLAG(td->td_proc, SV_ILP32)) { + /* + * We may be called for a 32bits process if we're using + * a 64bits debugger. If so, get PC and SPSR from where + * it put it. + */ + frame->tf_elr = regs->x[15]; + frame->tf_spsr = regs->x[16] & PSR_FLAGS; + } +#endif return (0); } @@ -283,8 +304,9 @@ fill_regs32(struct thread *td, struct reg32 *regs) tf = td->td_frame; for (i = 0; i < 13; i++) regs->r[i] = tf->tf_x[i]; - regs->r_sp = tf->tf_sp; - regs->r_lr = tf->tf_lr; + /* For arm32, SP is r13 and LR is r14 */ + regs->r_sp = tf->tf_x[13]; + regs->r_lr = tf->tf_x[14]; regs->r_pc = tf->tf_elr; regs->r_cpsr = tf->tf_spsr; @@ -300,8 +322,9 @@ set_regs32(struct thread *td, struct reg32 *regs) tf = td->td_frame; for (i = 0; i < 13; i++) tf->tf_x[i] = regs->r[i]; - tf->tf_sp = regs->r_sp; - tf->tf_lr = regs->r_lr; + /* For arm 32, SP is r13 an LR is r14 */ + tf->tf_x[13] = regs->r_sp; + tf->tf_x[14] = regs->r_lr; tf->tf_elr = regs->r_pc; tf->tf_spsr = regs->r_cpsr;