From owner-cvs-src-old@FreeBSD.ORG Fri Nov 26 21:16:33 2010 Return-Path: Delivered-To: cvs-src-old@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 21413106566B for ; Fri, 26 Nov 2010 21:16:33 +0000 (UTC) (envelope-from jkim@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id E859A8FC12 for ; Fri, 26 Nov 2010 21:16:32 +0000 (UTC) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.4/8.14.4) with ESMTP id oAQLGWZ2002900 for ; Fri, 26 Nov 2010 21:16:32 GMT (envelope-from jkim@repoman.freebsd.org) Received: (from svn2cvs@localhost) by repoman.freebsd.org (8.14.4/8.14.4/Submit) id oAQLGWAK002899 for cvs-src-old@freebsd.org; Fri, 26 Nov 2010 21:16:32 GMT (envelope-from jkim@repoman.freebsd.org) Message-Id: <201011262116.oAQLGWAK002899@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: svn2cvs set sender to jkim@repoman.freebsd.org using -f From: Jung-uk Kim Date: Fri, 26 Nov 2010 21:16:21 +0000 (UTC) To: cvs-src-old@freebsd.org X-FreeBSD-CVS-Branch: RELENG_8 Subject: cvs commit: src/sys/amd64/amd64 pmap.c src/sys/i386/i386 pmap.c X-BeenThere: cvs-src-old@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: **OBSOLETE** CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 26 Nov 2010 21:16:33 -0000 jkim 2010-11-26 21:16:21 UTC FreeBSD src repository Modified files: (Branch: RELENG_8) sys/amd64/amd64 pmap.c sys/i386/i386 pmap.c Log: SVN rev 215896 on 2010-11-26 21:16:21Z by jkim MFC: r196769, r196771, r211424, r215703, r215754 - Disable caches and flush caches/TLBs when we update PAT as we do for MTRR. Flushing TLBs is required to ensure cache coherency according to the AMD64 architecture manual. Flushing caches is only required when changing from a cacheable memory type (WB, WP or WT) to an uncacheable type (WC, UC or UC-). Since this function is only used once per processor during startup, there is no need to take any shortcuts. - Leave PAT indices 0-3 at the default of WB, WT, UC-, and UC. Program 5 as WP (from default WT) and 6 as WC (from default UC-). Leave 4 and 7 at the default of WB and UC. This is to avoid transition from a cacheable memory type to an uncacheable type to minimize possible cache incoherency. Since we perform flushing caches and TLBs now, this change may not be necessary any more but we do not want to take any chances. - Improve pmap_cache_bits() with an array to map PAT memory type to index. This array is initialized early from pmap_init_pat(), so that we do not need to handle special cases in the function any more. Now this function is identical on both amd64 and i386. Revision Changes Path 1.667.2.17 +83 -36 src/sys/amd64/amd64/pmap.c 1.645.2.21 +94 -87 src/sys/i386/i386/pmap.c