From owner-svn-src-head@FreeBSD.ORG Fri Apr 4 15:03:04 2014 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id B90B2AC1; Fri, 4 Apr 2014 15:03:04 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 89441A3E; Fri, 4 Apr 2014 15:03:04 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s34F341g043633; Fri, 4 Apr 2014 15:03:04 GMT (envelope-from ian@svn.freebsd.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s34F34Yj043632; Fri, 4 Apr 2014 15:03:04 GMT (envelope-from ian@svn.freebsd.org) Message-Id: <201404041503.s34F34Yj043632@svn.freebsd.org> From: Ian Lepore Date: Fri, 4 Apr 2014 15:03:04 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r264119 - head/sys/arm/ti X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Apr 2014 15:03:04 -0000 Author: ian Date: Fri Apr 4 15:03:03 2014 New Revision: 264119 URL: http://svnweb.freebsd.org/changeset/base/264119 Log: Adjust the comments about translating clock divisor bits to match recent code changes. Modified: head/sys/arm/ti/ti_sdhci.c Modified: head/sys/arm/ti/ti_sdhci.c ============================================================================== --- head/sys/arm/ti/ti_sdhci.c Fri Apr 4 14:54:54 2014 (r264118) +++ head/sys/arm/ti/ti_sdhci.c Fri Apr 4 15:03:03 2014 (r264119) @@ -167,13 +167,12 @@ ti_sdhci_read_2(device_t dev, struct sdh * but doesn't split them into low:high fields. Instead they're a * single number in the range 0..1023 and the number is exactly the * clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI - * driver code expects a v2.0 divisor (value N is power of two in the - * range 0..128 and clock is divided by 2N). The shifting and masking + * driver code expects a v2.0 or v3.0 divisor. The shifting and masking * here extracts the MMCHS representation from the hardware word, cleans - * those bits out, applies the 2N adjustment, and plugs that into the - * bit positions for the 2.0 divisor in the returned register value. The - * ti_sdhci_write_2() routine performs the opposite transformation when - * the SDHCI driver writes to the register. + * those bits out, applies the 2N adjustment, and plugs the result into + * the bit positions for the 2.0 or 3.0 divisor in the returned register + * value. The ti_sdhci_write_2() routine performs the opposite + * transformation when the SDHCI driver writes to the register. */ if (off == SDHCI_CLOCK_CONTROL) { val32 = RD4(sc, SDHCI_CLOCK_CONTROL); @@ -254,8 +253,9 @@ ti_sdhci_write_2(device_t dev, struct sd uint32_t clkdiv, val32; /* - * Translate between the hardware and SDHCI 2.0 representations of the - * clock divisor. See the comments in ti_sdhci_read_2() for details. + * Translate between the hardware and SDHCI 2.0 or 3.0 representations + * of the clock divisor. See the comments in ti_sdhci_read_2() for + * details. */ if (off == SDHCI_CLOCK_CONTROL) { clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK;