From owner-freebsd-current@FreeBSD.ORG Wed Jul 9 13:29:54 2003 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id BA87737B401 for ; Wed, 9 Jul 2003 13:29:54 -0700 (PDT) Received: from lerami.lerctr.org (lerami.lerctr.org [207.158.72.11]) by mx1.FreeBSD.org (Postfix) with ESMTP id C629343F3F for ; Wed, 9 Jul 2003 13:29:53 -0700 (PDT) (envelope-from ler@lerctr.org) Received: from lerlaptop-red.iadfw.net (lerlaptop-red.iadfw.net [207.136.3.72]) (authenticated bits=0)h69KTnag013436; Wed, 9 Jul 2003 15:29:50 -0500 (CDT) Date: Wed, 09 Jul 2003 15:29:43 -0500 From: Larry Rosenman To: Jens Rehsack , Brooks Davis Message-ID: <60470000.1057782583@lerlaptop-red.iadfw.net> In-Reply-To: <3F0C7A42.2080501@liwing.de> References: <20030708133504.L16193@pcle2.cc.univie.ac.at> <20030709123734.GA50458@nagual.pp.ru> <3F0C0ED6.4030202@liwing.de> <20030709150718.GC28375@Odin.AC.HMC.Edu> <3F0C7A42.2080501@liwing.de> X-Mailer: Mulberry/3.1.0b3 (Linux/x86) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline X-Virus-Scanned: by amavisd-milter (http://amavis.org/) cc: Andrey Chernov cc: freebsd-current@freebsd.org cc: Lukas Ertl Subject: Re: HTT on single CPU? X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Jul 2003 20:29:55 -0000 --On Wednesday, July 09, 2003 22:25:38 +0200 Jens Rehsack wrote: > Brooks Davis wrote: > >> >> P4's below ~3.1GHz do not actually provide logical CPU support. > > That's not true. German distributors sell P4 CPU's FSB 800 > (starting at 2.4GHz) which supports HTT. > > I know, that BSD didn't found 2 logical CPU's as John remarked, > but I didn't understood why the CPU has the feature for HTT but > no additional logical CPU's? ALL P-4's have the Feature Bit set, just not all of them have bits 23-16 of %ebx set to something greater than 1 on a cpuid instruction with %eax = 1. -- Larry Rosenman http://www.lerctr.org/~ler Phone: +1 972-414-9812 E-Mail: ler@lerctr.org US Mail: 1905 Steamboat Springs Drive, Garland, TX 75044-6749