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Date:      Wed, 25 Jul 2018 02:36:56 +0000 (UTC)
From:      David C Somayajulu <davidcs@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r336695 - in head/sys: dev/qlnx/qlnxe modules/qlnx modules/qlnx/qlnxe modules/qlnx/qlnxev
Message-ID:  <201807250236.w6P2au1l046734@repo.freebsd.org>

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Author: davidcs
Date: Wed Jul 25 02:36:55 2018
New Revision: 336695
URL: https://svnweb.freebsd.org/changeset/base/336695

Log:
  Remove support for QLNX_RCV_IN_TASKQ - i.e., Rx only in TaskQ.
  Added support for LLDP passthru
  Upgrade ECORE to version 8.33.5.0
  Upgrade STORMFW to version 8.33.7.0
  Added support for SRIOV
  
  MFC after:5 days

Added:
  head/sys/dev/qlnx/qlnxe/ecore_iwarp.h   (contents, props changed)
  head/sys/dev/qlnx/qlnxe/ecore_mng_tlv.c   (contents, props changed)
  head/sys/dev/qlnx/qlnxe/ecore_rdma.h   (contents, props changed)
  head/sys/dev/qlnx/qlnxe/ecore_rdma_api.h   (contents, props changed)
  head/sys/dev/qlnx/qlnxe/ecore_sriov.c   (contents, props changed)
  head/sys/dev/qlnx/qlnxe/ecore_tcp_ip.h   (contents, props changed)
  head/sys/dev/qlnx/qlnxe/ecore_vf.c   (contents, props changed)
  head/sys/modules/qlnx/qlnxev/
  head/sys/modules/qlnx/qlnxev/Makefile   (contents, props changed)
Modified:
  head/sys/dev/qlnx/qlnxe/bcm_osal.h
  head/sys/dev/qlnx/qlnxe/common_hsi.h
  head/sys/dev/qlnx/qlnxe/ecore.h
  head/sys/dev/qlnx/qlnxe/ecore_chain.h
  head/sys/dev/qlnx/qlnxe/ecore_cxt.c
  head/sys/dev/qlnx/qlnxe/ecore_cxt.h
  head/sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.c
  head/sys/dev/qlnx/qlnxe/ecore_dbg_fw_funcs.h
  head/sys/dev/qlnx/qlnxe/ecore_dbg_values.h
  head/sys/dev/qlnx/qlnxe/ecore_dcbx.c
  head/sys/dev/qlnx/qlnxe/ecore_dcbx.h
  head/sys/dev/qlnx/qlnxe/ecore_dcbx_api.h
  head/sys/dev/qlnx/qlnxe/ecore_dev.c
  head/sys/dev/qlnx/qlnxe/ecore_dev_api.h
  head/sys/dev/qlnx/qlnxe/ecore_fcoe.h
  head/sys/dev/qlnx/qlnxe/ecore_fcoe_api.h
  head/sys/dev/qlnx/qlnxe/ecore_hsi_common.h
  head/sys/dev/qlnx/qlnxe/ecore_hsi_debug_tools.h
  head/sys/dev/qlnx/qlnxe/ecore_hsi_eth.h
  head/sys/dev/qlnx/qlnxe/ecore_hsi_fcoe.h
  head/sys/dev/qlnx/qlnxe/ecore_hsi_init_func.h
  head/sys/dev/qlnx/qlnxe/ecore_hsi_init_tool.h
  head/sys/dev/qlnx/qlnxe/ecore_hsi_iscsi.h
  head/sys/dev/qlnx/qlnxe/ecore_hsi_iwarp.h
  head/sys/dev/qlnx/qlnxe/ecore_hsi_rdma.h
  head/sys/dev/qlnx/qlnxe/ecore_hsi_roce.h
  head/sys/dev/qlnx/qlnxe/ecore_hw.c
  head/sys/dev/qlnx/qlnxe/ecore_hw.h
  head/sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c
  head/sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.h
  head/sys/dev/qlnx/qlnxe/ecore_init_ops.c
  head/sys/dev/qlnx/qlnxe/ecore_init_values.h
  head/sys/dev/qlnx/qlnxe/ecore_int.c
  head/sys/dev/qlnx/qlnxe/ecore_int.h
  head/sys/dev/qlnx/qlnxe/ecore_int_api.h
  head/sys/dev/qlnx/qlnxe/ecore_iov_api.h
  head/sys/dev/qlnx/qlnxe/ecore_iro.h
  head/sys/dev/qlnx/qlnxe/ecore_iro_values.h
  head/sys/dev/qlnx/qlnxe/ecore_iscsi.h
  head/sys/dev/qlnx/qlnxe/ecore_iscsi_api.h
  head/sys/dev/qlnx/qlnxe/ecore_l2.c
  head/sys/dev/qlnx/qlnxe/ecore_l2.h
  head/sys/dev/qlnx/qlnxe/ecore_l2_api.h
  head/sys/dev/qlnx/qlnxe/ecore_ll2.h
  head/sys/dev/qlnx/qlnxe/ecore_ll2_api.h
  head/sys/dev/qlnx/qlnxe/ecore_mcp.c
  head/sys/dev/qlnx/qlnxe/ecore_mcp.h
  head/sys/dev/qlnx/qlnxe/ecore_mcp_api.h
  head/sys/dev/qlnx/qlnxe/ecore_ooo.h
  head/sys/dev/qlnx/qlnxe/ecore_proto_if.h
  head/sys/dev/qlnx/qlnxe/ecore_roce.h
  head/sys/dev/qlnx/qlnxe/ecore_roce_api.h
  head/sys/dev/qlnx/qlnxe/ecore_rt_defs.h
  head/sys/dev/qlnx/qlnxe/ecore_sp_commands.c
  head/sys/dev/qlnx/qlnxe/ecore_sp_commands.h
  head/sys/dev/qlnx/qlnxe/ecore_spq.c
  head/sys/dev/qlnx/qlnxe/ecore_spq.h
  head/sys/dev/qlnx/qlnxe/ecore_sriov.h
  head/sys/dev/qlnx/qlnxe/ecore_utils.h
  head/sys/dev/qlnx/qlnxe/ecore_vf.h
  head/sys/dev/qlnx/qlnxe/ecore_vf_api.h
  head/sys/dev/qlnx/qlnxe/ecore_vfpf_if.h
  head/sys/dev/qlnx/qlnxe/eth_common.h
  head/sys/dev/qlnx/qlnxe/fcoe_common.h
  head/sys/dev/qlnx/qlnxe/iscsi_common.h
  head/sys/dev/qlnx/qlnxe/mcp_private.h
  head/sys/dev/qlnx/qlnxe/mcp_public.h
  head/sys/dev/qlnx/qlnxe/nvm_cfg.h
  head/sys/dev/qlnx/qlnxe/nvm_map.h
  head/sys/dev/qlnx/qlnxe/qlnx_def.h
  head/sys/dev/qlnx/qlnxe/qlnx_ioctl.c
  head/sys/dev/qlnx/qlnxe/qlnx_ioctl.h
  head/sys/dev/qlnx/qlnxe/qlnx_os.c
  head/sys/dev/qlnx/qlnxe/qlnx_os.h
  head/sys/dev/qlnx/qlnxe/qlnx_ver.h
  head/sys/dev/qlnx/qlnxe/rdma_common.h
  head/sys/dev/qlnx/qlnxe/reg_addr.h
  head/sys/dev/qlnx/qlnxe/roce_common.h
  head/sys/dev/qlnx/qlnxe/spad_layout.h
  head/sys/dev/qlnx/qlnxe/storage_common.h
  head/sys/dev/qlnx/qlnxe/tcp_common.h
  head/sys/modules/qlnx/Makefile
  head/sys/modules/qlnx/qlnxe/Makefile

Modified: head/sys/dev/qlnx/qlnxe/bcm_osal.h
==============================================================================
--- head/sys/dev/qlnx/qlnxe/bcm_osal.h	Wed Jul 25 01:04:50 2018	(r336694)
+++ head/sys/dev/qlnx/qlnxe/bcm_osal.h	Wed Jul 25 02:36:55 2018	(r336695)
@@ -34,7 +34,7 @@
 #include "ecore_status.h"
 #include <sys/bitstring.h>
 
-#if __FreeBSD_version >= 1200000
+#if __FreeBSD_version >= 1200032
 #include <linux/bitmap.h>
 #else
 #if __FreeBSD_version >= 1100090
@@ -62,6 +62,7 @@ extern void qlnx_pci_write_config_word(void *ecore_dev
 extern void qlnx_pci_write_config_dword(void *ecore_dev, uint32_t pci_reg,
                         uint32_t reg_value);
 extern int qlnx_pci_find_capability(void *ecore_dev, int cap);
+extern int qlnx_pci_find_ext_capability(void *ecore_dev, int ext_cap);
 
 extern uint32_t qlnx_direct_reg_rd32(void *p_hwfn, uint32_t *reg_addr);
 extern void qlnx_direct_reg_wr32(void *p_hwfn, void *reg_addr, uint32_t value);
@@ -72,6 +73,7 @@ extern void qlnx_reg_wr32(void *p_hwfn, uint32_t reg_a
 extern void qlnx_reg_wr16(void *p_hwfn, uint32_t reg_addr, uint16_t value);
 
 extern void qlnx_dbell_wr32(void *p_hwfn, uint32_t reg_addr, uint32_t value);
+extern void qlnx_dbell_wr32_db(void *p_hwfn, void *reg_addr, uint32_t value);
 
 extern void *qlnx_dma_alloc_coherent(void *ecore_dev, bus_addr_t *phys,
                         uint32_t size);
@@ -89,6 +91,16 @@ extern void qlnx_get_protocol_stats(void *cdev, int pr
 extern void qlnx_sp_isr(void *arg);
 
 
+extern void qlnx_osal_vf_fill_acquire_resc_req(void *p_hwfn, void *p_resc_req,
+			void *p_sw_info);
+extern void qlnx_osal_iov_vf_cleanup(void *p_hwfn, uint8_t relative_vf_id);
+extern int qlnx_iov_chk_ucast(void *p_hwfn, int vfid, void *params);
+extern int qlnx_iov_update_vport(void *p_hwfn, uint8_t vfid, void *params,
+		uint16_t *tlvs);
+extern int qlnx_pf_vf_msg(void *p_hwfn, uint16_t relative_vf_id);
+extern void qlnx_vf_flr_update(void *p_hwfn);
+
+#define nothing			do {} while(0)
 #ifdef ECORE_PACKAGE
 
 /* Memory Types */
@@ -130,7 +142,6 @@ rounddown_pow_of_two(unsigned long x)
 	((type)(val1) < (type)(val2) ? (type)(val1) : (val2))
 
 #define ARRAY_SIZE(arr)		(sizeof(arr) / sizeof(arr[0]))
-#define nothing			do {} while(0)
 #define BUILD_BUG_ON(cond)	nothing
 
 #endif /* #ifndef QLNX_RDMA */
@@ -209,6 +220,7 @@ typedef struct osal_list_t
 #define DIRECT_REG_WR(p_hwfn, addr, value) qlnx_direct_reg_wr32(p_hwfn, addr, value)
 #define DIRECT_REG_WR64(p_hwfn, addr, value) \
 		qlnx_direct_reg_wr64(p_hwfn, addr, value)
+#define DIRECT_REG_WR_DB(p_hwfn, addr, value) qlnx_dbell_wr32_db(p_hwfn, addr, value)
 #define DIRECT_REG_RD(p_hwfn, addr) qlnx_direct_reg_rd32(p_hwfn, addr)
 #define REG_RD(hwfn, addr) qlnx_reg_rd32(hwfn, addr)
 #define DOORBELL(hwfn, addr, value) \
@@ -238,7 +250,8 @@ typedef struct osal_list_t
 
 #define OSAL_DPC_ALLOC(hwfn) malloc(PAGE_SIZE, M_QLNXBUF, M_NOWAIT)
 #define OSAL_DPC_INIT(dpc, hwfn) nothing
-#define OSAL_SCHEDULE_RECOVERY_HANDLER(x) nothing
+extern void qlnx_schedule_recovery(void *p_hwfn);
+#define OSAL_SCHEDULE_RECOVERY_HANDLER(x) do {qlnx_schedule_recovery(x);} while(0)
 #define OSAL_HW_ERROR_OCCURRED(hwfn, err_type) nothing
 #define OSAL_DPC_SYNC(hwfn) nothing
 
@@ -371,7 +384,9 @@ do {							\
 #define OSAL_PCI_WRITE_CONFIG_DWORD(dev, reg, value) \
 		qlnx_pci_write_config_dword(dev, reg, value);
 
-#define OSAL_PCI_FIND_CAPABILITY(dev, cap) qlnx_pci_find_capability(dev, cap);
+#define OSAL_PCI_FIND_CAPABILITY(dev, cap) qlnx_pci_find_capability(dev, cap)
+#define OSAL_PCI_FIND_EXT_CAPABILITY(dev, ext_cap) \
+				qlnx_pci_find_ext_capability(dev, ext_cap)
 
 #define OSAL_MMIOWB(dev) qlnx_barrier(dev)
 #define OSAL_BARRIER(dev) qlnx_barrier(dev)
@@ -390,8 +405,7 @@ do {							\
 #define OSAL_FIND_FIRST_ZERO_BIT(bitmap, length) \
 		find_first_zero_bit(bitmap, length)
 
-#define OSAL_LINK_UPDATE(hwfn) qlnx_link_update(hwfn)
-#define OSAL_VF_FLR_UPDATE(hwfn)
+#define OSAL_LINK_UPDATE(hwfn, ptt) qlnx_link_update(hwfn)
 
 #define QLNX_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
 #define QLNX_ROUNDUP(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
@@ -536,8 +550,36 @@ OSAL_CRC8(u8 * cdu_crc8_table, u8 * data_to_crc, int d
 
 #define OSAL_HW_INFO_CHANGE(p_hwfn, offset)
 #define OSAL_MFW_TLV_REQ(p_hwfn)
-#define OSAL_VF_FILL_ACQUIRE_RESC_REQ(p_hwfn, req, vf_sw_info) {};
+#define OSAL_LLDP_RX_TLVS(p_hwfn, buffer, len)
+#define OSAL_MFW_CMD_PREEMPT(p_hwfn)
+#define OSAL_TRANSCEIVER_UPDATE(p_hwfn)
+#define OSAL_MFW_FILL_TLV_DATA(p_hwfn, group, data) (0)
+
 #define OSAL_VF_UPDATE_ACQUIRE_RESC_RESP(p_hwfn, res) (0)
+
+#define OSAL_VF_FILL_ACQUIRE_RESC_REQ(p_hwfn, req, vf_sw_info) \
+		qlnx_osal_vf_fill_acquire_resc_req(p_hwfn, req, vf_sw_info)
+
+#define OSAL_IOV_PF_RESP_TYPE(p_hwfn, relative_vf_id, status)
+#define OSAL_IOV_VF_CLEANUP(p_hwfn, relative_vf_id) \
+		qlnx_osal_iov_vf_cleanup(p_hwfn, relative_vf_id)
+
+#define OSAL_IOV_VF_ACQUIRE(p_hwfn, relative_vf_id) ECORE_SUCCESS
+#define OSAL_IOV_GET_OS_TYPE()	VFPF_ACQUIRE_OS_FREEBSD
+#define OSAL_IOV_PRE_START_VPORT(p_hwfn, relative_vf_id, params) ECORE_SUCCESS
+#define OSAL_IOV_POST_START_VPORT(p_hwfn, relative_vf_id, vport_id, opaque_fid) 
+#define OSAL_PF_VALIDATE_MODIFY_TUNN_CONFIG(p_hwfn, x, y, z) ECORE_SUCCESS
+#define OSAL_IOV_CHK_UCAST(p_hwfn, vfid, params) \
+			qlnx_iov_chk_ucast(p_hwfn, vfid, params);
+#define OSAL_PF_VF_MALICIOUS(p_hwfn, relative_vf_id) 
+#define OSAL_IOV_VF_MSG_TYPE(p_hwfn, relative_vf_id, type)
+#define OSAL_IOV_VF_VPORT_UPDATE(p_hwfn, vfid, params, tlvs) \
+		qlnx_iov_update_vport(p_hwfn, vfid, params, tlvs)
+#define OSAL_PF_VF_MSG(p_hwfn, relative_vf_id) \
+		qlnx_pf_vf_msg(p_hwfn, relative_vf_id)
+
+#define OSAL_VF_FLR_UPDATE(p_hwfn) qlnx_vf_flr_update(p_hwfn)
+#define OSAL_IOV_VF_VPORT_STOP(p_hwfn, vf)
 
 #endif /* #ifdef ECORE_PACKAGE */
 

Modified: head/sys/dev/qlnx/qlnxe/common_hsi.h
==============================================================================
--- head/sys/dev/qlnx/qlnxe/common_hsi.h	Wed Jul 25 01:04:50 2018	(r336694)
+++ head/sys/dev/qlnx/qlnxe/common_hsi.h	Wed Jul 25 02:36:55 2018	(r336695)
@@ -104,8 +104,8 @@
 
 
 #define FW_MAJOR_VERSION		8
-#define FW_MINOR_VERSION		30
-#define FW_REVISION_VERSION		0
+#define FW_MINOR_VERSION		33
+#define FW_REVISION_VERSION		7
 #define FW_ENGINEERING_VERSION	0
 
 /***********************/
@@ -113,76 +113,69 @@
 /***********************/
 
 /* PCI functions */
-#define MAX_NUM_PORTS_BB		(2)
-#define MAX_NUM_PORTS_K2		(4)
-#define MAX_NUM_PORTS_E5		(MAX_NUM_PORTS_K2)
-#define MAX_NUM_PORTS			(MAX_NUM_PORTS_E5)
+#define MAX_NUM_PORTS_BB        (2)
+#define MAX_NUM_PORTS_K2        (4)
+#define MAX_NUM_PORTS_E5        (4)
+#define MAX_NUM_PORTS           (MAX_NUM_PORTS_E5)
 
-#define MAX_NUM_PFS_BB			(8)
-#define MAX_NUM_PFS_K2			(16)
-#define MAX_NUM_PFS_E5			(MAX_NUM_PFS_K2)
-#define MAX_NUM_PFS				(MAX_NUM_PFS_E5)
-#define MAX_NUM_OF_PFS_IN_CHIP	(16) /* On both engines */
+#define MAX_NUM_PFS_BB          (8)
+#define MAX_NUM_PFS_K2          (16)
+#define MAX_NUM_PFS_E5          (16)
+#define MAX_NUM_PFS             (MAX_NUM_PFS_E5)
+#define MAX_NUM_OF_PFS_IN_CHIP  (16) /* On both engines */
 
-#define MAX_NUM_VFS_BB			(120)
-#define MAX_NUM_VFS_K2			(192)
-#define MAX_NUM_VFS_E4			(MAX_NUM_VFS_K2)
-#define MAX_NUM_VFS_E5			(240)
-#define COMMON_MAX_NUM_VFS		(MAX_NUM_VFS_E5)
+#define MAX_NUM_VFS_BB          (120)
+#define MAX_NUM_VFS_K2          (192)
+#define MAX_NUM_VFS_E4          (MAX_NUM_VFS_K2)
+#define MAX_NUM_VFS_E5          (240)
+#define COMMON_MAX_NUM_VFS      (MAX_NUM_VFS_E5)
 
-#define MAX_NUM_FUNCTIONS_BB	(MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
-#define MAX_NUM_FUNCTIONS_K2	(MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2)
-#define MAX_NUM_FUNCTIONS		(MAX_NUM_PFS + MAX_NUM_VFS_E4)
+#define MAX_NUM_FUNCTIONS_BB    (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
+#define MAX_NUM_FUNCTIONS_K2    (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2)
+#define MAX_NUM_FUNCTIONS       (MAX_NUM_PFS + MAX_NUM_VFS_E4)
 
 /* in both BB and K2, the VF number starts from 16. so for arrays containing all */
 /* possible PFs and VFs - we need a constant for this size */
-#define MAX_FUNCTION_NUMBER_BB	(MAX_NUM_PFS + MAX_NUM_VFS_BB)
-#define MAX_FUNCTION_NUMBER_K2	(MAX_NUM_PFS + MAX_NUM_VFS_K2)
-#define MAX_FUNCTION_NUMBER_E4	(MAX_NUM_PFS + MAX_NUM_VFS_E4)
-#define MAX_FUNCTION_NUMBER_E5	(MAX_NUM_PFS + MAX_NUM_VFS_E5)
-#define COMMON_MAX_FUNCTION_NUMBER	(MAX_NUM_PFS + MAX_NUM_VFS_E5)
+#define MAX_FUNCTION_NUMBER_BB      (MAX_NUM_PFS + MAX_NUM_VFS_BB)
+#define MAX_FUNCTION_NUMBER_K2      (MAX_NUM_PFS + MAX_NUM_VFS_K2)
+#define MAX_FUNCTION_NUMBER_E4      (MAX_NUM_PFS + MAX_NUM_VFS_E4)
+#define MAX_FUNCTION_NUMBER_E5      (MAX_NUM_PFS + MAX_NUM_VFS_E5)
+#define COMMON_MAX_FUNCTION_NUMBER  (MAX_NUM_PFS + MAX_NUM_VFS_E5)
 
-#define MAX_NUM_VPORTS_K2		(208)
-#define MAX_NUM_VPORTS_BB		(160)
-#define MAX_NUM_VPORTS_E4		(MAX_NUM_VPORTS_K2)
-#define MAX_NUM_VPORTS_E5		(256)
-#define COMMON_MAX_NUM_VPORTS	(MAX_NUM_VPORTS_E5)
+#define MAX_NUM_VPORTS_K2       (208)
+#define MAX_NUM_VPORTS_BB       (160)
+#define MAX_NUM_VPORTS_E4       (MAX_NUM_VPORTS_K2)
+#define MAX_NUM_VPORTS_E5       (256)
+#define COMMON_MAX_NUM_VPORTS   (MAX_NUM_VPORTS_E5)
 
-#define MAX_NUM_L2_QUEUES_K2	(320)
 #define MAX_NUM_L2_QUEUES_BB	(256)
-#define MAX_NUM_L2_QUEUES		(MAX_NUM_L2_QUEUES_K2)
+#define MAX_NUM_L2_QUEUES_K2    (320)
+#define MAX_NUM_L2_QUEUES_E5    (320) /* TODO_E5_VITALY - fix to 512 */
+#define MAX_NUM_L2_QUEUES		(MAX_NUM_L2_QUEUES_E5)
 
 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */
-#define NUM_PHYS_TCS_4PORT_K2	(4)
-#define NUM_PHYS_TCS_4PORT_E5	(6)
-#define NUM_OF_PHYS_TCS			(8)
-#define PURE_LB_TC				NUM_OF_PHYS_TCS
-#define NUM_TCS_4PORT_K2		(NUM_PHYS_TCS_4PORT_K2 + 1)
-#define NUM_TCS_4PORT_E5		(NUM_PHYS_TCS_4PORT_E5 + 1)
-#define NUM_OF_TCS				(NUM_OF_PHYS_TCS + 1)
+#define NUM_PHYS_TCS_4PORT_K2     4
+#define NUM_PHYS_TCS_4PORT_TX_E5  6
+#define NUM_PHYS_TCS_4PORT_RX_E5  4
+#define NUM_OF_PHYS_TCS           8
+#define PURE_LB_TC                NUM_OF_PHYS_TCS
+#define NUM_TCS_4PORT_K2          (NUM_PHYS_TCS_4PORT_K2 + 1)
+#define NUM_TCS_4PORT_TX_E5       (NUM_PHYS_TCS_4PORT_TX_E5 + 1)
+#define NUM_TCS_4PORT_RX_E5       (NUM_PHYS_TCS_4PORT_RX_E5 + 1)
+#define NUM_OF_TCS                (NUM_OF_PHYS_TCS + 1)
 
-/* Num of possible traffic priority values */
-#define NUM_OF_PRIO				(8)
-
 /* CIDs */
 #define NUM_OF_CONNECTION_TYPES_E4 (8)
 #define NUM_OF_CONNECTION_TYPES_E5 (16)
-#define NUM_OF_TASK_TYPES		(8)
-#define NUM_OF_LCIDS			(320)
-#define NUM_OF_LTIDS			(320)
+#define NUM_OF_TASK_TYPES       (8)
+#define NUM_OF_LCIDS            (320)
+#define NUM_OF_LTIDS            (320)
 
-/* Clock values */
-#define MASTER_CLK_FREQ_E4		(375e6)
-#define STORM_CLK_FREQ_E4		(1000e6)
-#define CLK25M_CLK_FREQ_E4		(25e6)
-
-#define STORM_CLK_DUAL_CORE_FREQ_E5 (3000e6)
-
 /* Global PXP windows (GTT) */
-#define NUM_OF_GTT			19
-#define GTT_DWORD_SIZE_BITS	10
-#define GTT_BYTE_SIZE_BITS	(GTT_DWORD_SIZE_BITS + 2)
-#define GTT_DWORD_SIZE		(1 << GTT_DWORD_SIZE_BITS)
+#define NUM_OF_GTT          19
+#define GTT_DWORD_SIZE_BITS 10
+#define GTT_BYTE_SIZE_BITS  (GTT_DWORD_SIZE_BITS + 2)
+#define GTT_DWORD_SIZE      (1 << GTT_DWORD_SIZE_BITS)
 
 /* Tools Version */
 #define TOOLS_VERSION 10
@@ -417,7 +410,7 @@
 /* Number of Protocol Indices per Status Block */
 #define PIS_PER_SB_E4    12
 #define PIS_PER_SB_E5    8
-#define MAX_PIS_PER_SB	 OSAL_MAX_T(u8, PIS_PER_SB_E4, PIS_PER_SB_E5)
+#define MAX_PIS_PER_SB	 OSAL_MAX_T(PIS_PER_SB_E4,PIS_PER_SB_E5)
 
 
 #define CAU_HC_STOPPED_STATE		3			/* fsm is stopped or not valid for this sb */
@@ -548,10 +541,6 @@
 /* VF BAR */
 #define PXP_VF_BAR0                             0
 
-#define PXP_VF_BAR0_START_GRC                   0x3E00
-#define PXP_VF_BAR0_GRC_LENGTH                  0x200
-#define PXP_VF_BAR0_END_GRC                     (PXP_VF_BAR0_START_GRC + PXP_VF_BAR0_GRC_LENGTH - 1)
-
 #define PXP_VF_BAR0_START_IGU                   0
 #define PXP_VF_BAR0_IGU_LENGTH                  0x3000
 #define PXP_VF_BAR0_END_IGU                     (PXP_VF_BAR0_START_IGU + PXP_VF_BAR0_IGU_LENGTH - 1)
@@ -582,9 +571,17 @@
 #define PXP_VF_BAR0_START_PSDM_ZONE_B           0x3c00
 #define PXP_VF_BAR0_END_PSDM_ZONE_B             (PXP_VF_BAR0_START_PSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
 
+#define PXP_VF_BAR0_START_GRC                   0x3E00
+#define PXP_VF_BAR0_GRC_LENGTH                  0x200
+#define PXP_VF_BAR0_END_GRC                     (PXP_VF_BAR0_START_GRC + PXP_VF_BAR0_GRC_LENGTH - 1)
+
 #define PXP_VF_BAR0_START_SDM_ZONE_A            0x4000
 #define PXP_VF_BAR0_END_SDM_ZONE_A              0x10000
 
+#define PXP_VF_BAR0_START_IGU2                   0x10000
+#define PXP_VF_BAR0_IGU2_LENGTH                  0xD000
+#define PXP_VF_BAR0_END_IGU2                     (PXP_VF_BAR0_START_IGU2 + PXP_VF_BAR0_IGU2_LENGTH - 1)
+
 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH           32
 
 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN          12
@@ -593,15 +590,16 @@
 // ILT Records
 #define PXP_NUM_ILT_RECORDS_BB 7600
 #define PXP_NUM_ILT_RECORDS_K2 11000
-#define MAX_NUM_ILT_RECORDS OSAL_MAX_T(u16, PXP_NUM_ILT_RECORDS_BB,PXP_NUM_ILT_RECORDS_K2)
+#define MAX_NUM_ILT_RECORDS OSAL_MAX_T(PXP_NUM_ILT_RECORDS_BB,PXP_NUM_ILT_RECORDS_K2)
 
+#define PXP_NUM_ILT_RECORDS_E5 13664
 
+
 // Host Interface
-#define PXP_QUEUES_ZONE_MAX_NUM	320
+#define PXP_QUEUES_ZONE_MAX_NUM_E4	320
+#define PXP_QUEUES_ZONE_MAX_NUM_E5	512
 
 
-
-
 /*****************/
 /* PRM CONSTANTS */
 /*****************/
@@ -651,18 +649,6 @@
 #define PRS_GFT_CAM_LINES_NO_MATCH  31
 
 /*
- * Async data KCQ CQE 
- */
-struct async_data
-{
-	__le32 cid /* Context ID of the connection */;
-	__le16 itid /* Task Id of the task (for error that happened on a a task) */;
-	u8 error_code /* error code - relevant only if the opcode indicates its an error */;
-	u8 fw_debug_param /* internal fw debug parameter */;
-};
-
-
-/*
  * Interrupt coalescing TimeSet
  */
 struct coalescing_timeset
@@ -692,24 +678,30 @@ struct eth_rx_prod_data
 };
 
 
-struct regpair
+struct tcp_ulp_connect_done_params
 {
-	__le32 lo /* low word for reg-pair */;
-	__le32 hi /* high word for reg-pair */;
+	__le16 mss;
+	u8 snd_wnd_scale;
+	u8 flags;
+#define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK     0x1
+#define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT    0
+#define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK  0x7F
+#define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_SHIFT 1
 };
 
-/*
- * Event Ring VF-PF Channel data
- */
-struct vf_pf_channel_eqe_data
+struct iscsi_connect_done_results
 {
-	struct regpair msg_addr /* VF-PF message address */;
+	__le16 icid /* Context ID of the connection */;
+	__le16 conn_id /* Driver connection ID */;
+	struct tcp_ulp_connect_done_params params /* decided tcp params after connect done */;
 };
 
+
 struct iscsi_eqe_data
 {
-	__le32 cid /* Context ID of the connection */;
-	__le16 conn_id /* Task Id of the task (for error that happened on a a task) */;
+	__le16 icid /* Context ID of the connection */;
+	__le16 conn_id /* Driver connection ID */;
+	__le16 reserved;
 	u8 error_code /* error code - relevant only if the opcode indicates its an error */;
 	u8 error_pdu_opcode_reserved;
 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK        0x3F /* The processed PDUs opcode on which happened the error - updated for specific error codes, by defualt=0xFF */
@@ -720,80 +712,8 @@ struct iscsi_eqe_data
 #define ISCSI_EQE_DATA_RESERVED0_SHIFT              7
 };
 
-/*
- * RoCE Destroy Event Data
- */
-struct rdma_eqe_destroy_qp
-{
-	__le32 cid /* Dedicated field RoCE destroy QP event */;
-	u8 reserved[4];
-};
 
 /*
- * RDMA Event Data Union
- */
-union rdma_eqe_data
-{
-	struct regpair async_handle /* Host handle for the Async Completions */;
-	struct rdma_eqe_destroy_qp rdma_destroy_qp_data /* RoCE Destroy Event Data */;
-};
-
-/*
- * Event Ring malicious VF data
- */
-struct malicious_vf_eqe_data
-{
-	u8 vf_id /* Malicious VF ID */;
-	u8 err_id /* Malicious VF error */;
-	__le16 reserved[3];
-};
-
-/*
- * Event Ring initial cleanup data
- */
-struct initial_cleanup_eqe_data
-{
-	u8 vf_id /* VF ID */;
-	u8 reserved[7];
-};
-
-/*
- * Event Data Union
- */
-union event_ring_data
-{
-	u8 bytes[8] /* Byte Array */;
-	struct vf_pf_channel_eqe_data vf_pf_channel /* VF-PF Channel data */;
-	struct iscsi_eqe_data iscsi_info /* Dedicated fields to iscsi data */;
-	union rdma_eqe_data rdma_data /* Dedicated field for RDMA data */;
-	struct malicious_vf_eqe_data malicious_vf /* Malicious VF data */;
-	struct initial_cleanup_eqe_data vf_init_cleanup /* VF Initial Cleanup data */;
-};
-
-
-/*
- * Event Ring Entry
- */
-struct event_ring_entry
-{
-	u8 protocol_id /* Event Protocol ID */;
-	u8 opcode /* Event Opcode */;
-	__le16 reserved0 /* Reserved */;
-	__le16 echo /* Echo value from ramrod data on the host */;
-	u8 fw_return_code /* FW return code for SP ramrods */;
-	u8 flags;
-#define EVENT_RING_ENTRY_ASYNC_MASK      0x1 /* 0: synchronous EQE - a completion of SP message. 1: asynchronous EQE */
-#define EVENT_RING_ENTRY_ASYNC_SHIFT     0
-#define EVENT_RING_ENTRY_RESERVED1_MASK  0x7F
-#define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
-	union event_ring_data data;
-};
-
-
-
-
-
-/*
  * Multi function mode
  */
 enum mf_mode
@@ -824,9 +744,34 @@ enum protocol_type
 };
 
 
+struct regpair
+{
+	__le32 lo /* low word for reg-pair */;
+	__le32 hi /* high word for reg-pair */;
+};
 
+/*
+ * RoCE Destroy Event Data
+ */
+struct rdma_eqe_destroy_qp
+{
+	__le32 cid /* Dedicated field RoCE destroy QP event */;
+	u8 reserved[4];
+};
 
 /*
+ * RDMA Event Data Union
+ */
+union rdma_eqe_data
+{
+	struct regpair async_handle /* Host handle for the Async Completions */;
+	struct rdma_eqe_destroy_qp rdma_destroy_qp_data /* RoCE Destroy Event Data */;
+};
+
+
+
+
+/*
  * Ustorm Queue Zone
  */
 struct ustorm_eth_queue_zone
@@ -843,7 +788,6 @@ struct ustorm_queue_zone
 };
 
 
-
 /*
  * status block structure
  */
@@ -894,6 +838,17 @@ struct cau_sb_entry
 
 
 /*
+ * Igu cleanup bit values to distinguish between clean or producer consumer update.
+ */
+enum command_type_bit
+{
+	IGU_COMMAND_TYPE_NOP=0,
+	IGU_COMMAND_TYPE_SET=1,
+	MAX_COMMAND_TYPE_BIT
+};
+
+
+/*
  * core doorbell data
  */
 struct core_db_data
@@ -1339,90 +1294,74 @@ struct pxp_vf_zone_a_permission
  */
 struct rdif_task_context
 {
-	__le32 initialRefTag;
-	__le16 appTagValue;
-	__le16 appTagMask;
+	__le32 initial_ref_tag;
+	__le16 app_tag_value;
+	__le16 app_tag_mask;
 	u8 flags0;
-#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK            0x1
-#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT           0
-#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK      0x1
-#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT     1
-#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK           0x1 /* 0 = IP checksum, 1 = CRC */
-#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT          2
-#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK         0x1
-#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT        3
-#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK          0x3 /* 1/2/3 - Protection Type */
-#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT         4
-#define RDIF_TASK_CONTEXT_CRC_SEED_MASK                0x1 /* 0=0x0000, 1=0xffff */
-#define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT               6
-#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK         0x1 /* Keep reference tag constant */
-#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT        7
-	u8 partialDifData[7];
-	__le16 partialCrcValue;
-	__le16 partialChecksumValue;
-	__le32 offsetInIO;
+#define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK             0x1
+#define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT            0
+#define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK      0x1
+#define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT     1
+#define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK            0x1 /* 0 = IP checksum, 1 = CRC */
+#define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT           2
+#define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK         0x1
+#define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT        3
+#define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK            0x3 /* 1/2/3 - Protection Type */
+#define RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT           4
+#define RDIF_TASK_CONTEXT_CRC_SEED_MASK                   0x1 /* 0=0x0000, 1=0xffff */
+#define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT                  6
+#define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK         0x1 /* Keep reference tag constant */
+#define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT        7
+	u8 partial_dif_data[7];
+	__le16 partial_crc_value;
+	__le16 partial_checksum_value;
+	__le32 offset_in_io;
 	__le16 flags1;
-#define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK           0x1
-#define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT          0
-#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK          0x1
-#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT         1
-#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK          0x1
-#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT         2
-#define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK            0x1
-#define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT           3
-#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK           0x1
-#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT          4
-#define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK           0x1
-#define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT          5
-#define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK            0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */
-#define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT           6
-#define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK           0x3 /* 0=None, 1=DIF, 2=DIX */
-#define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT          9
-#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK           0x1 /* DIF tag right at the beginning of DIF interval */
-#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT          11
-#define RDIF_TASK_CONTEXT_RESERVED0_MASK               0x1
-#define RDIF_TASK_CONTEXT_RESERVED0_SHIFT              12
-#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK        0x1 /* 0=None, 1=DIF */
-#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT       13
-#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK   0x1 /* Forward application tag with mask */
-#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT  14
-#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK   0x1 /* Forward reference tag with mask */
-#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT  15
+#define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK             0x1
+#define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT            0
+#define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK           0x1
+#define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT          1
+#define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK           0x1
+#define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT          2
+#define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK              0x1
+#define RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT             3
+#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK            0x1
+#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT           4
+#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK            0x1
+#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT           5
+#define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK              0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */
+#define RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT             6
+#define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK             0x3 /* 0=None, 1=DIF, 2=DIX */
+#define RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT            9
+#define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK            0x1 /* DIF tag right at the beginning of DIF interval */
+#define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT           11
+#define RDIF_TASK_CONTEXT_RESERVED0_MASK                  0x1
+#define RDIF_TASK_CONTEXT_RESERVED0_SHIFT                 12
+#define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK          0x1 /* 0=None, 1=DIF */
+#define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT         13
+#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK  0x1 /* Forward application tag with mask */
+#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 14
+#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK  0x1 /* Forward reference tag with mask */
+#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 15
 	__le16 state;
-#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK    0xF
-#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT   0
-#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK  0xF
-#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4
-#define RDIF_TASK_CONTEXT_ERRORINIO_MASK               0x1
-#define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT              8
-#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK        0x1
-#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT       9
-#define RDIF_TASK_CONTEXT_REFTAGMASK_MASK              0xF /* mask for refernce tag handling */
-#define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT             10
-#define RDIF_TASK_CONTEXT_RESERVED1_MASK               0x3
-#define RDIF_TASK_CONTEXT_RESERVED1_SHIFT              14
+#define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK    0xF
+#define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT   0
+#define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK  0xF
+#define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT 4
+#define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK                0x1
+#define RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT               8
+#define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK          0x1
+#define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT         9
+#define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK               0xF /* mask for refernce tag handling */
+#define RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT              10
+#define RDIF_TASK_CONTEXT_RESERVED1_MASK                  0x3
+#define RDIF_TASK_CONTEXT_RESERVED1_SHIFT                 14
 	__le32 reserved2;
 };
 
 
 
 /*
- * RSS hash type
- */
-enum rss_hash_type
-{
-	RSS_HASH_TYPE_DEFAULT=0,
-	RSS_HASH_TYPE_IPV4=1,
-	RSS_HASH_TYPE_TCP_IPV4=2,
-	RSS_HASH_TYPE_IPV6=3,
-	RSS_HASH_TYPE_TCP_IPV6=4,
-	RSS_HASH_TYPE_UDP_IPV4=5,
-	RSS_HASH_TYPE_UDP_IPV6=6,
-	MAX_RSS_HASH_TYPE
-};
-
-
-/*
  * status block structure
  */
 struct status_block_e4
@@ -1469,85 +1408,85 @@ struct status_block_e5
  */
 struct tdif_task_context
 {
-	__le32 initialRefTag;
-	__le16 appTagValue;
-	__le16 appTagMask;
-	__le16 partialCrcValueB;
-	__le16 partialChecksumValueB;
+	__le32 initial_ref_tag;
+	__le16 app_tag_value;
+	__le16 app_tag_mask;
+	__le16 partial_crc_value_b;
+	__le16 partial_checksum_value_b;
 	__le16 stateB;
-#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK    0xF
-#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT   0
-#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK  0xF
-#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4
-#define TDIF_TASK_CONTEXT_ERRORINIOB_MASK               0x1
-#define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT              8
-#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK         0x1
-#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT        9
-#define TDIF_TASK_CONTEXT_RESERVED0_MASK                0x3F
-#define TDIF_TASK_CONTEXT_RESERVED0_SHIFT               10
+#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK    0xF
+#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT   0
+#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK  0xF
+#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT 4
+#define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK                0x1
+#define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT               8
+#define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK             0x1
+#define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT            9
+#define TDIF_TASK_CONTEXT_RESERVED0_MASK                    0x3F
+#define TDIF_TASK_CONTEXT_RESERVED0_SHIFT                   10
 	u8 reserved1;
 	u8 flags0;
-#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK             0x1
-#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT            0
-#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK       0x1
-#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT      1
-#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK            0x1 /* 0 = IP checksum, 1 = CRC */
-#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT           2
-#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK          0x1
-#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT         3
-#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK           0x3 /* 1/2/3 - Protection Type */
-#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT          4
-#define TDIF_TASK_CONTEXT_CRC_SEED_MASK                 0x1 /* 0=0x0000, 1=0xffff */
-#define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT                6
-#define TDIF_TASK_CONTEXT_RESERVED2_MASK                0x1
-#define TDIF_TASK_CONTEXT_RESERVED2_SHIFT               7
+#define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK               0x1
+#define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT              0
+#define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK        0x1
+#define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT       1
+#define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK              0x1 /* 0 = IP checksum, 1 = CRC */
+#define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT             2
+#define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK           0x1
+#define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT          3
+#define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK              0x3 /* 1/2/3 - Protection Type */
+#define TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT             4
+#define TDIF_TASK_CONTEXT_CRC_SEED_MASK                     0x1 /* 0=0x0000, 1=0xffff */
+#define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT                    6
+#define TDIF_TASK_CONTEXT_RESERVED2_MASK                    0x1
+#define TDIF_TASK_CONTEXT_RESERVED2_SHIFT                   7
 	__le32 flags1;
-#define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK            0x1
-#define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT           0
-#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK           0x1
-#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT          1
-#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK           0x1
-#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT          2
-#define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK             0x1
-#define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT            3
-#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK            0x1
-#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT           4
-#define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK            0x1
-#define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT           5
-#define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK             0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */
-#define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT            6
-#define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK            0x3 /* 0=None, 1=DIF, 2=DIX */
-#define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT           9
-#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK            0x1 /* DIF tag right at the beginning of DIF interval */
-#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT           11
-#define TDIF_TASK_CONTEXT_RESERVED3_MASK                0x1 /* reserved */
-#define TDIF_TASK_CONTEXT_RESERVED3_SHIFT               12
-#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK         0x1 /* 0=None, 1=DIF */
-#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT        13
-#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK    0xF
-#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT   14
-#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK  0xF
-#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18
-#define TDIF_TASK_CONTEXT_ERRORINIOA_MASK               0x1
-#define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT              22
-#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK        0x1
-#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT       23
-#define TDIF_TASK_CONTEXT_REFTAGMASK_MASK               0xF /* mask for refernce tag handling */
-#define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT              24
-#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK    0x1 /* Forward application tag with mask */
-#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT   28
-#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK    0x1 /* Forward reference tag with mask */
-#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT   29
-#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK          0x1 /* Keep reference tag constant */
-#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT         30
-#define TDIF_TASK_CONTEXT_RESERVED4_MASK                0x1
-#define TDIF_TASK_CONTEXT_RESERVED4_SHIFT               31
-	__le32 offsetInIOB;
-	__le16 partialCrcValueA;
-	__le16 partialChecksumValueA;
-	__le32 offsetInIOA;
-	u8 partialDifDataA[8];
-	u8 partialDifDataB[8];
+#define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK               0x1
+#define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT              0
+#define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK             0x1
+#define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT            1
+#define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK             0x1
+#define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT            2
+#define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK                0x1
+#define TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT               3
+#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK              0x1
+#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT             4
+#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK              0x1
+#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT             5
+#define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK                0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */
+#define TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT               6
+#define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK               0x3 /* 0=None, 1=DIF, 2=DIX */
+#define TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT              9
+#define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK              0x1 /* DIF tag right at the beginning of DIF interval */
+#define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT             11
+#define TDIF_TASK_CONTEXT_RESERVED3_MASK                    0x1 /* reserved */
+#define TDIF_TASK_CONTEXT_RESERVED3_SHIFT                   12
+#define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK            0x1 /* 0=None, 1=DIF */
+#define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT           13
+#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK    0xF
+#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT   14
+#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK  0xF
+#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT 18
+#define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK                0x1
+#define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT               22
+#define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK          0x1
+#define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT         23
+#define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK                 0xF /* mask for refernce tag handling */
+#define TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT                24
+#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK    0x1 /* Forward application tag with mask */
+#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT   28
+#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK    0x1 /* Forward reference tag with mask */
+#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT   29
+#define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK           0x1 /* Keep reference tag constant */
+#define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT          30
+#define TDIF_TASK_CONTEXT_RESERVED4_MASK                    0x1
+#define TDIF_TASK_CONTEXT_RESERVED4_SHIFT                   31
+	__le32 offset_in_io_b;
+	__le16 partial_crc_value_a;
+	__le16 partial_checksum_value_a;
+	__le32 offset_in_io_a;
+	u8 partial_dif_data_a[8];
+	u8 partial_dif_data_b[8];
 };
 
 
@@ -1602,7 +1541,7 @@ struct timers_context
 
 
 /*
- * Enum for next_protocol field of tunnel_parsing_flags
+ * Enum for next_protocol field of tunnel_parsing_flags / tunnelTypeDesc
  */
 enum tunnel_next_protocol
 {

Modified: head/sys/dev/qlnx/qlnxe/ecore.h
==============================================================================
--- head/sys/dev/qlnx/qlnxe/ecore.h	Wed Jul 25 01:04:50 2018	(r336694)
+++ head/sys/dev/qlnx/qlnxe/ecore.h	Wed Jul 25 02:36:55 2018	(r336695)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018 Cavium, Inc. 
+ * Copyright (c) 2017-2018 Cavium, Inc.
  * All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
@@ -31,6 +31,7 @@
 #ifndef __ECORE_H
 #define __ECORE_H
 
+#include "ecore_status.h"
 #include "ecore_hsi_common.h"
 #include "ecore_hsi_debug_tools.h"
 #include "ecore_hsi_init_func.h"
@@ -39,8 +40,8 @@
 #include "mcp_public.h"
 
 #define ECORE_MAJOR_VERSION		8
-#define ECORE_MINOR_VERSION		30
-#define ECORE_REVISION_VERSION		0
+#define ECORE_MINOR_VERSION		33
+#define ECORE_REVISION_VERSION		5
 #define ECORE_ENGINEERING_VERSION	0
 
 #define ECORE_VERSION							\
@@ -58,6 +59,7 @@
 
 /* Constants */
 #define ECORE_WID_SIZE		(1024)
+#define ECORE_MIN_WIDS		(4)
 
 /* Configurable */
 #define ECORE_PF_DEMS_SIZE	(4)
@@ -80,11 +82,14 @@ enum ecore_nvm_cmd {
 	ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE,
 	ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ,
 	ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE,
+	ECORE_ENCRYPT_PASSWORD = DRV_MSG_CODE_ENCRYPT_PASSWORD,
 	ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00
 };
 
+#ifndef LINUX_REMOVE
 #if !defined(CONFIG_ECORE_L2) && !defined(CONFIG_ECORE_ROCE) && \
-    !defined(CONFIG_ECORE_FCOE) && !defined(CONFIG_ECORE_ISCSI)
+	!defined(CONFIG_ECORE_FCOE) && !defined(CONFIG_ECORE_ISCSI) && \
+	!defined(CONFIG_ECORE_IWARP)
 #define CONFIG_ECORE_L2
 #define CONFIG_ECORE_SRIOV
 #define CONFIG_ECORE_ROCE
@@ -93,8 +98,10 @@ enum ecore_nvm_cmd {
 #define CONFIG_ECORE_ISCSI
 #define CONFIG_ECORE_LL2
 #endif
+#endif
 
 /* helpers */
+#ifndef __EXTRACT__LINUX__IF__
 #define MASK_FIELD(_name, _value)					\
 		((_value) &= (_name##_MASK))
 
@@ -115,9 +122,10 @@ do {									\
 
 #define SET_MFW_FIELD(name, field, value)				\
 do {									\
-	(name) &= ~((field ## _MASK) << (field ## _OFFSET));		\
+	(name) &= ~(field ## _MASK);					\
 	(name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK));	\
 } while (0)
+#endif
 
 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS)
 {
@@ -139,6 +147,7 @@ static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
 	((sizeof(type_name) + (u32)(1<<(p_hwfn->p_dev->cache_shift))-1) & \
 	 ~((1<<(p_hwfn->p_dev->cache_shift))-1))
 
+#ifndef LINUX_REMOVE
 #ifndef U64_HI
 #define U64_HI(val) ((u32)(((u64)(val))  >> 32))
 #endif
@@ -146,7 +155,9 @@ static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS)
 #ifndef U64_LO
 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff))
 #endif
+#endif
 
+#ifndef __EXTRACT__LINUX__IF__
 #ifndef UEFI
 /* Debug print definitions */
 #define DP_ERR(p_dev, fmt, ...)				\
@@ -203,6 +214,7 @@ enum DP_LEVEL {
 #define ECORE_LOG_NOTICE_MASK	(0x80000000)
 
 enum DP_MODULE {
+#ifndef LINUX_REMOVE
 	ECORE_MSG_DRV		= 0x0001,
 	ECORE_MSG_PROBE		= 0x0002,
 	ECORE_MSG_LINK		= 0x0004,
@@ -218,6 +230,7 @@ enum DP_MODULE {
 	ECORE_MSG_PKTDATA	= 0x1000,
 	ECORE_MSG_HW		= 0x2000,
 	ECORE_MSG_WOL		= 0x4000,
+#endif
 	ECORE_MSG_SPQ		= 0x10000,
 	ECORE_MSG_STATS		= 0x20000,
 	ECORE_MSG_DCB		= 0x40000,
@@ -232,6 +245,7 @@ enum DP_MODULE {
 	ECORE_MSG_DEBUG		= 0x8000000,
 	/* to be added...up to 0x8000000 */
 };
+#endif
 
 #define for_each_hwfn(p_dev, i)	for (i = 0; i < p_dev->num_hwfns; i++)
 
@@ -252,6 +266,7 @@ struct ecore_l2_info;
 struct ecore_igu_info;
 struct ecore_mcp_info;
 struct ecore_dcbx_info;
+struct ecore_llh_info;
 
 struct ecore_rt_data {
 	u32	*init_val;
@@ -321,6 +336,15 @@ struct ecore_qm_iids {
 	u32 tids;
 };
 
+/* The PCI relax ordering is either taken care by management FW or can be
+ * enable/disable by ecore client.
+ */
+enum ecore_pci_rlx_odr {
+	ECORE_DEFAULT_RLX_ODR,
+	ECORE_ENABLE_RLX_ODR,
+	ECORE_DISABLE_RLX_ODR
+};
+
 #define MAX_PF_PER_PORT 8
 
 /* HW / FW resources, output of features supported below, most information
@@ -387,6 +411,7 @@ enum ecore_dev_cap {
 	ECORE_DEV_CAP_IWARP
 };
 
+#ifndef __EXTRACT__LINUX__IF__
 enum ecore_hw_err_type {
 	ECORE_HW_ERR_FAN_FAIL,
 	ECORE_HW_ERR_MFW_RESP_FAIL,
@@ -395,6 +420,7 @@ enum ecore_hw_err_type {
 	ECORE_HW_ERR_RAMROD_FAIL,
 	ECORE_HW_ERR_FW_ASSERT,
 };
+#endif

*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***



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