Date: Sun, 1 Jul 2001 15:52:56 +0300 From: Valentin Nechayev <netch@iv.nn.kiev.ua> To: "E.B. Dreger" <eddy+public+spam@noc.everquick.net> Cc: Bernd Walter <ticso@mail.cicely.de>, freebsd-smp@FreeBSD.ORG, freebsd-hackers@FreeBSD.ORG Subject: Re: libc_r locking... why? Message-ID: <20010701155256.C376@iv.nn.kiev.ua> In-Reply-To: <Pine.LNX.4.20.0106291940590.13439-100000@www.everquick.net>; from eddy%2Bpublic%2Bspam@noc.everquick.net on Fri, Jun 29, 2001 at 07:56:40PM %2B0000 References: <20010629211818.A17309@cicely20.cicely.de> <Pine.LNX.4.20.0106291940590.13439-100000@www.everquick.net>
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Fri, Jun 29, 2001 at 19:56:40, eddy+public+spam (E.B. Dreger) wrote about "Re: libc_r locking... why?": > > A Token may not be enough because writes may be reordered. AFAIK it's false for i386 architecture. Please correct me if needed. > Here is where I want to learn more about cache coherency, inter-processor > interrupts, and APIC programming. I'd imagine that the latter two are > lower-level than I'd be using, but I still want to know the "how and why" > beneath the scenes. Did you try to read MP chipsets white papers? /netch To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-smp" in the body of the message
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