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From: Ian Lepore <ian@FreeBSD.org>
Date: Fri, 4 Apr 2014 17:39:05 +0000 (UTC)
To: src-committers@freebsd.org, svn-src-all@freebsd.org,
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Subject: svn commit: r264128 - head/sys/arm/arm
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Author: ian
Date: Fri Apr  4 17:39:05 2014
New Revision: 264128
URL: http://svnweb.freebsd.org/changeset/base/264128

Log:
  Fix TTB set operation for armv7.
  
  Perform sychronization (by "isb" barrier) after TTB is set.  This
  is done to ensure that TLB invalidation always executes after
  TTB modification and operates on valid CP15 data (per specification).
  
  Submitted by:	Wojciech Macek <wma@semihalf.com>
  Reviewed by:	ian@, cognet@

Modified:
  head/sys/arm/arm/cpufunc_asm_armv7.S

Modified: head/sys/arm/arm/cpufunc_asm_armv7.S
==============================================================================
--- head/sys/arm/arm/cpufunc_asm_armv7.S	Fri Apr  4 17:01:49 2014	(r264127)
+++ head/sys/arm/arm/cpufunc_asm_armv7.S	Fri Apr  4 17:39:05 2014	(r264128)
@@ -71,6 +71,7 @@ ENTRY(armv7_setttb)
 				
 	orr 	r0, r0, #PT_ATTR
  	mcr	p15, 0, r0, c2, c0, 0	/* Translation Table Base Register 0 (TTBR0) */
+	isb
 #ifdef SMP
  	mcr     p15, 0, r0, c8, c3, 0   /* invalidate I+D TLBs Inner Shareable*/
 #else
@@ -273,6 +274,7 @@ ENTRY(armv7_context_switch)
 	orr     r0, r0, #PT_ATTR
 			
 	mcr	p15, 0, r0, c2, c0, 0	/* set the new TTB */
+	isb
 #ifdef SMP
 	mcr	p15, 0, r0, c8, c3, 0	/* and flush the I+D tlbs Inner Sharable */
 #else