From owner-freebsd-amd64@FreeBSD.ORG Tue Jul 17 16:04:19 2012 Return-Path: Delivered-To: freebsd-amd64@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 52016106564A for ; Tue, 17 Jul 2012 16:04:19 +0000 (UTC) (envelope-from brde@optusnet.com.au) Received: from fallbackmx08.syd.optusnet.com.au (fallbackmx08.syd.optusnet.com.au [211.29.132.10]) by mx1.freebsd.org (Postfix) with ESMTP id D81998FC08 for ; Tue, 17 Jul 2012 16:04:18 +0000 (UTC) Received: from mail07.syd.optusnet.com.au (mail07.syd.optusnet.com.au [211.29.132.188]) by fallbackmx08.syd.optusnet.com.au (8.13.1/8.13.1) with ESMTP id q6HG4CTF026574 for ; Wed, 18 Jul 2012 02:04:12 +1000 Received: from c122-106-171-246.carlnfd1.nsw.optusnet.com.au (c122-106-171-246.carlnfd1.nsw.optusnet.com.au [122.106.171.246]) by mail07.syd.optusnet.com.au (8.13.1/8.13.1) with ESMTP id q6HG3wOl012957 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 18 Jul 2012 02:04:04 +1000 Date: Wed, 18 Jul 2012 02:03:58 +1000 (EST) From: Bruce Evans X-X-Sender: bde@besplex.bde.org To: Bruce Evans In-Reply-To: <20120718011942.D7642@besplex.bde.org> Message-ID: <20120718014222.V7761@besplex.bde.org> References: <201207171350.q6HDoAJS033797@freefall.freebsd.org> <20120717235622.C7417@besplex.bde.org> <20120718011942.D7642@besplex.bde.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed Cc: freebsd-amd64@FreeBSD.org Subject: Re: amd64/169927: siginfo, si_code for fpe errors when error occurs using the SSE math processor X-BeenThere: freebsd-amd64@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the AMD64 platform List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Jul 2012 16:04:19 -0000 On Wed, 18 Jul 2012, Bruce Evans wrote: > On Wed, 18 Jul 2012, Bruce Evans wrote: >> .. >> So I still want a single kernel exception handle that merges the statuses. > > Merge the independent statuses modified by their independent controls: > > return (fpetable[(fpsw & ((~fpcw & 0x3f) | 0x40)) | > ((mxcsr & (mxcsr >> 16)) & 0x3f)]); > > Use the same trap handler that reads all these statuses and controls. Changed my mind again. Need sleep. Merging the traps breaks the rule that i387 traps occur on the first non-control instruction after the one that causes the exception. There may be mixed code like this: fldz fld1 fdiv %st,%st(1) # i387 exception now; i387 trap pending load $0 into %xmm0 load $1 into %xmm1 divsd %xmm0,%xmm1 # SSE exception now; SSE trap now Debuggers can see both exception states including the i387 trap pending, provided the i387 trap is not bogusly cleared, either by never clearing it in the kernel trap handler or by using a separate trap handler that doesn't clear it for T_XMMFLT. They can even figure out that an SSE trap occurred, because the i387 trap is still pending. ... fnop # i387 trap on first non-control FP instr... Apart from doing the bogus fnclex for T_XMMFLT and the delayed effect of i387 status bits, merging or not merging the statuses makes little difference, since if a status bit is set and is not masked according to its control word, then it will generate a trap soon if it didn't genearate the current one. Bruce