From owner-svn-src-head@freebsd.org Sun Sep 3 08:32:34 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 6C451E21AB4; Sun, 3 Sep 2017 08:32:34 +0000 (UTC) (envelope-from mw@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 36E3A2DB9; Sun, 3 Sep 2017 08:32:34 +0000 (UTC) (envelope-from mw@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v838WXdT080472; Sun, 3 Sep 2017 08:32:33 GMT (envelope-from mw@FreeBSD.org) Received: (from mw@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v838WXth080470; Sun, 3 Sep 2017 08:32:33 GMT (envelope-from mw@FreeBSD.org) Message-Id: <201709030832.v838WXth080470@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: mw set sender to mw@FreeBSD.org using -f From: Marcin Wojtas Date: Sun, 3 Sep 2017 08:32:33 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r323138 - in head/sys/arm64: arm64 include X-SVN-Group: head X-SVN-Commit-Author: mw X-SVN-Commit-Paths: in head/sys/arm64: arm64 include X-SVN-Commit-Revision: 323138 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 03 Sep 2017 08:32:34 -0000 Author: mw Date: Sun Sep 3 08:32:33 2017 New Revision: 323138 URL: https://svnweb.freebsd.org/changeset/base/323138 Log: Add ARM Cortex A72 to CPU list This change is required to properly detect CPUs on Marvell Armada 80x0/70x0 SoC family. Submitted by: Rafal Kozik Reviewed by: andrew, cognet (mentor) Approved by: cognet (mentor) Sponsored by: Semihalf Differential Revision: https://reviews.freebsd.org/D12184 Modified: head/sys/arm64/arm64/identcpu.c head/sys/arm64/include/cpu.h Modified: head/sys/arm64/arm64/identcpu.c ============================================================================== --- head/sys/arm64/arm64/identcpu.c Sun Sep 3 06:43:08 2017 (r323137) +++ head/sys/arm64/arm64/identcpu.c Sun Sep 3 08:32:33 2017 (r323138) @@ -122,6 +122,7 @@ static const struct cpu_parts cpu_parts_arm[] = { { CPU_PART_FOUNDATION, "Foundation-Model" }, { CPU_PART_CORTEX_A53, "Cortex-A53" }, { CPU_PART_CORTEX_A57, "Cortex-A57" }, + { CPU_PART_CORTEX_A72, "Cortex-A72" }, CPU_PART_NONE, }; /* Cavium */ Modified: head/sys/arm64/include/cpu.h ============================================================================== --- head/sys/arm64/include/cpu.h Sun Sep 3 06:43:08 2017 (r323137) +++ head/sys/arm64/include/cpu.h Sun Sep 3 08:32:33 2017 (r323138) @@ -82,6 +82,7 @@ #define CPU_PART_FOUNDATION 0xD00 #define CPU_PART_CORTEX_A53 0xD03 #define CPU_PART_CORTEX_A57 0xD07 +#define CPU_PART_CORTEX_A72 0xD08 #define CPU_REV_THUNDER_1_0 0x00 #define CPU_REV_THUNDER_1_1 0x01