From owner-svn-src-head@freebsd.org Thu Dec 28 21:46:10 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id AAAD0E82975; Thu, 28 Dec 2017 21:46:10 +0000 (UTC) (envelope-from marius@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 74CBD6DB48; Thu, 28 Dec 2017 21:46:10 +0000 (UTC) (envelope-from marius@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id vBSLk9J3033653; Thu, 28 Dec 2017 21:46:09 GMT (envelope-from marius@FreeBSD.org) Received: (from marius@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id vBSLk9Uo033652; Thu, 28 Dec 2017 21:46:09 GMT (envelope-from marius@FreeBSD.org) Message-Id: <201712282146.vBSLk9Uo033652@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: marius set sender to marius@FreeBSD.org using -f From: Marius Strobl Date: Thu, 28 Dec 2017 21:46:09 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r327314 - head/sys/x86/x86 X-SVN-Group: head X-SVN-Commit-Author: marius X-SVN-Commit-Paths: head/sys/x86/x86 X-SVN-Commit-Revision: 327314 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Dec 2017 21:46:10 -0000 Author: marius Date: Thu Dec 28 21:46:09 2017 New Revision: 327314 URL: https://svnweb.freebsd.org/changeset/base/327314 Log: With the advent of interrupt remapping, Intel has repurposed bit 11 (now: Interrupt_Index[15]) and assigned the previously reserved bits 55:48 (Interrupt_Index[14:0] goes into 63:49 while Destination Field used 63:56 and bit 48 now is Interrupt_Format) in the IO redirection tables (see the VT-d specification, "5.1.5.1 I/OxAPIC Programming"). Thus, when not using interrupt remapping, ensure that all previously reserved bits in the high part of the RTEs are zero instead of doing a read-modify-write for their Destination Field bits only. Otherwise, on machines based on Apollo Lake and its derivatives such as Denverton, typically some of the previously preserved bits remain set after boot when not employing interrupt remapping. The result is that INTx interrupts are not getting delivered. Note: With an AMD IOMMU, interrupt remapping apparently bypasses the IO APIC altogether. Submitted by: loos (modulo comment) Reviewed by: jhb (modulo comment) Modified: head/sys/x86/x86/io_apic.c Modified: head/sys/x86/x86/io_apic.c ============================================================================== --- head/sys/x86/x86/io_apic.c Thu Dec 28 21:35:53 2017 (r327313) +++ head/sys/x86/x86/io_apic.c Thu Dec 28 21:46:09 2017 (r327314) @@ -308,7 +308,7 @@ static void ioapic_program_intpin(struct ioapic_intsrc *intpin) { struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic; - uint32_t low, high, value; + uint32_t low, high; #ifdef ACPI_DMAR int error; #endif @@ -354,7 +354,11 @@ ioapic_program_intpin(struct ioapic_intsrc *intpin) } #endif - /* Set the destination. */ + /* + * Set the destination. Note that with Intel interrupt remapping, + * the previously reserved bits 55:48 now have a purpose so ensure + * these are zero. + */ low = IOART_DESTPHY; high = intpin->io_cpu << APIC_ID_SHIFT; @@ -392,10 +396,7 @@ ioapic_program_intpin(struct ioapic_intsrc *intpin) } /* Write the values to the APIC. */ - value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin)); - value &= ~IOART_DEST; - value |= high; - ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value); + ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), high); intpin->io_lowreg = low; ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low); }