From owner-svn-src-user@FreeBSD.ORG Thu Apr 15 05:24:19 2010 Return-Path: Delivered-To: svn-src-user@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 0FF61106567A; Thu, 15 Apr 2010 05:24:19 +0000 (UTC) (envelope-from jmallett@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 9BF3B8FC1E; Thu, 15 Apr 2010 05:24:18 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o3F5OIrH097705; Thu, 15 Apr 2010 05:24:18 GMT (envelope-from jmallett@svn.freebsd.org) Received: (from jmallett@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o3F5OIfr097699; Thu, 15 Apr 2010 05:24:18 GMT (envelope-from jmallett@svn.freebsd.org) Message-Id: <201004150524.o3F5OIfr097699@svn.freebsd.org> From: Juli Mallett Date: Thu, 15 Apr 2010 05:24:18 +0000 (UTC) To: src-committers@freebsd.org, svn-src-user@freebsd.org X-SVN-Group: user MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r206645 - in user/jmallett/octeon/sys/mips: cavium mips X-BeenThere: svn-src-user@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the experimental " user" src tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Apr 2010 05:24:19 -0000 Author: jmallett Date: Thu Apr 15 05:24:18 2010 New Revision: 206645 URL: http://svn.freebsd.org/changeset/base/206645 Log: o) Make APs on Octeon wait to be awoken. o) Use CLEAR_STATUS rather than moving zero to the status register. o) Awaken APs on Octeon. XXX This blows up somewhere around setting up dpcpu stuff. Probably either the TLB wiring isn't being done right or we're not clearing BEV and so some unrelated TLB load is blowing up? Modified: user/jmallett/octeon/sys/mips/cavium/asm_octeon.S user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c user/jmallett/octeon/sys/mips/cavium/octeon_mp.c user/jmallett/octeon/sys/mips/mips/locore.S user/jmallett/octeon/sys/mips/mips/mpboot.S Modified: user/jmallett/octeon/sys/mips/cavium/asm_octeon.S ============================================================================== --- user/jmallett/octeon/sys/mips/cavium/asm_octeon.S Thu Apr 15 02:59:21 2010 (r206644) +++ user/jmallett/octeon/sys/mips/cavium/asm_octeon.S Thu Apr 15 05:24:18 2010 (r206645) @@ -25,15 +25,42 @@ * * $FreeBSD$ */ + #include + .set noreorder + #ifdef SMP /* * This function must be implemented in assembly because it is called early * in AP boot without a valid stack. */ LEAF(platform_processor_id) - li v0, 0 + .set push + .set mips32r2 jr ra + rdhwr v0, $0 + .set pop END(platform_processor_id) + +/* + * Called on APs to wait until they are told to launch. + */ +LEAF(octeon_ap_wait) + jal platform_processor_id + nop + +1: ll t0, octeon_ap_boot + bne v0, t0, 1b + nop + + move t0, zero + sc t0, octeon_ap_boot + + beqz t0, 1b + nop + + j mpentry + nop +END(octeon_ap_wait) #endif Modified: user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c ============================================================================== --- user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c Thu Apr 15 02:59:21 2010 (r206644) +++ user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c Thu Apr 15 05:24:18 2010 (r206645) @@ -834,7 +834,7 @@ octeon_boot_params_init(register_t ptr) printf("Boot Descriptor Ver: %u -> %u/%u", octeon_bd_ver, octeon_cvmx_bd_ver/100, octeon_cvmx_bd_ver%100); - printf(" CPU clock: %uMHz\n", octeon_cpu_clock/1000000); + printf(" CPU clock: %uMHz Core Mask: %#x\n", octeon_cpu_clock/1000000, octeon_core_mask); printf(" Dram: %u MB", (uint32_t)(octeon_dram >> 20)); printf(" Board Type: %u Revision: %u/%u\n", octeon_board_type, octeon_board_rev_major, octeon_board_rev_minor); Modified: user/jmallett/octeon/sys/mips/cavium/octeon_mp.c ============================================================================== --- user/jmallett/octeon/sys/mips/cavium/octeon_mp.c Thu Apr 15 02:59:21 2010 (r206644) +++ user/jmallett/octeon/sys/mips/cavium/octeon_mp.c Thu Apr 15 05:24:18 2010 (r206645) @@ -36,6 +36,10 @@ __FBSDID("$FreeBSD$"); #include #include +#include + +unsigned octeon_ap_boot = ~0; + void platform_ipi_send(int cpuid) { @@ -51,25 +55,29 @@ platform_ipi_clear(void) int platform_ipi_intrnum(void) { - panic("%s: not yet implemented.", __func__); + return (1); } void platform_init_ap(int cpuid) { - panic("%s: not yet implemented.", __func__); - - KASSERT(cpuid == 1, ("AP has an invalid cpu id %d", cpuid)); } int platform_num_processors(void) { - panic("%s: not yet implemented.", __func__); + return (fls(octeon_core_mask)); } int platform_start_ap(int cpuid) { - panic("%s: not yet implemented.", __func__); + if (atomic_cmpset_32(&octeon_ap_boot, ~0, cpuid) == 0) + return (-1); + for (;;) { + DELAY(1000); + if (atomic_cmpset_32(&octeon_ap_boot, 0, ~0) != 0) + return (0); + printf("Waiting for cpu%d to start\n", cpuid); + } } Modified: user/jmallett/octeon/sys/mips/mips/locore.S ============================================================================== --- user/jmallett/octeon/sys/mips/mips/locore.S Thu Apr 15 02:59:21 2010 (r206644) +++ user/jmallett/octeon/sys/mips/mips/locore.S Thu Apr 15 05:24:18 2010 (r206645) @@ -162,6 +162,18 @@ VECTOR(_locore, unknown) sw a2, _C_LABEL(fenvp) #endif +#if defined(TARGET_OCTEON) && defined(SMP) + .set push + .set mips32r2 + rdhwr t2, $0 + beqz t2, 1f + nop + j octeon_ap_wait + nop + .set pop +1: +#endif + /* * Initialize stack and call machine startup. */ Modified: user/jmallett/octeon/sys/mips/mips/mpboot.S ============================================================================== --- user/jmallett/octeon/sys/mips/mips/mpboot.S Thu Apr 15 02:59:21 2010 (r206644) +++ user/jmallett/octeon/sys/mips/mips/mpboot.S Thu Apr 15 05:24:18 2010 (r206645) @@ -36,9 +36,24 @@ .set noat .set noreorder +#ifdef TARGET_OCTEON +#define CLEAR_STATUS \ + mfc0 a0, COP_0_STATUS_REG ;\ + li a2, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \ + or a0, a0, a2 ; \ + li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER) ; \ + and a0, a0, a2 ; \ + mtc0 a0, COP_0_STATUS_REG +#else +#define CLEAR_STATUS \ + mfc0 a0, COP_0_STATUS_REG ;\ + li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER) ; \ + and a0, a0, a2 ; \ + mtc0 a0, COP_0_STATUS_REG +#endif + GLOBAL(mpentry) - /* XXX On n64 this will be a problem. */ - mtc0 zero, COP_0_STATUS_REG /* disable interrupts */ + CLEAR_STATUS /* disable interrupts */ mtc0 zero, COP_0_CAUSE_REG /* clear soft interrupts */