From owner-svn-src-head@freebsd.org Sat May 4 17:35:15 2019 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 4BE66159429E; Sat, 4 May 2019 17:35:15 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id E12A06A90D; Sat, 4 May 2019 17:35:14 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id C5A8DB863; Sat, 4 May 2019 17:35:14 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x44HZET6035829; Sat, 4 May 2019 17:35:14 GMT (envelope-from cem@FreeBSD.org) Received: (from cem@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x44HZErV035827; Sat, 4 May 2019 17:35:14 GMT (envelope-from cem@FreeBSD.org) Message-Id: <201905041735.x44HZErV035827@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: cem set sender to cem@FreeBSD.org using -f From: Conrad Meyer Date: Sat, 4 May 2019 17:35:14 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r347129 - in head/sys: amd64/include i386/include x86/x86 X-SVN-Group: head X-SVN-Commit-Author: cem X-SVN-Commit-Paths: in head/sys: amd64/include i386/include x86/x86 X-SVN-Commit-Revision: 347129 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: E12A06A90D X-Spamd-Bar: -- Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-2.95 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_MEDIUM(-1.00)[-0.999,0]; NEURAL_HAM_LONG(-1.00)[-1.000,0]; NEURAL_HAM_SHORT(-0.95)[-0.949,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 04 May 2019 17:35:15 -0000 Author: cem Date: Sat May 4 17:35:13 2019 New Revision: 347129 URL: https://svnweb.freebsd.org/changeset/base/347129 Log: x86: Define pc_monitorbuf as a logical structure Rather than just accessing it via pointer cast. No functional change intended. Discussed with: kib (earlier version) Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D20135 Modified: head/sys/amd64/include/pcpu.h head/sys/i386/include/pcpu.h head/sys/x86/x86/cpu_machdep.c Modified: head/sys/amd64/include/pcpu.h ============================================================================== --- head/sys/amd64/include/pcpu.h Sat May 4 16:27:58 2019 (r347128) +++ head/sys/amd64/include/pcpu.h Sat May 4 17:35:13 2019 (r347129) @@ -36,6 +36,13 @@ #endif #define PC_PTI_STACK_SZ 16 + +struct monitorbuf { + int idle_state; /* Used by cpu_idle_mwait. */ + char padding[128 - (1 * sizeof(int))]; +}; +_Static_assert(sizeof(struct monitorbuf) == 128, "2x cache line"); + /* * The SMP parts are setup in pmap.c and locore.s for the BSP, and * mp_machdep.c sets up the data for the AP's to "see" when they awake. @@ -44,7 +51,7 @@ * other processors" */ #define PCPU_MD_FIELDS \ - char pc_monitorbuf[128] __aligned(128); /* cache line */ \ + struct monitorbuf pc_monitorbuf __aligned(128); /* cache line */\ struct pcpu *pc_prvspace; /* Self-reference */ \ struct pmap *pc_curpmap; \ struct amd64tss *pc_tssp; /* TSS segment active on CPU */ \ Modified: head/sys/i386/include/pcpu.h ============================================================================== --- head/sys/i386/include/pcpu.h Sat May 4 16:27:58 2019 (r347128) +++ head/sys/i386/include/pcpu.h Sat May 4 17:35:13 2019 (r347129) @@ -41,6 +41,12 @@ #include #include +struct monitorbuf { + int idle_state; /* Used by cpu_idle_mwait. */ + char padding[128 - (1 * sizeof(int))]; +}; +_Static_assert(sizeof(struct monitorbuf) == 128, "2x cache line"); + /* * The SMP parts are setup in pmap.c and machdep.c for the BSP, and * pmap.c and mp_machdep.c sets up the data for the AP's to "see" when @@ -50,7 +56,7 @@ */ #define PCPU_MD_FIELDS \ - char pc_monitorbuf[128] __aligned(128); /* cache line */ \ + struct monitorbuf pc_monitorbuf __aligned(128); /* cache line */\ struct pcpu *pc_prvspace; /* Self-reference */ \ struct pmap *pc_curpmap; \ struct segment_descriptor pc_common_tssd; \ Modified: head/sys/x86/x86/cpu_machdep.c ============================================================================== --- head/sys/x86/x86/cpu_machdep.c Sat May 4 16:27:58 2019 (r347128) +++ head/sys/x86/x86/cpu_machdep.c Sat May 4 17:35:13 2019 (r347129) @@ -164,7 +164,7 @@ acpi_cpu_idle_mwait(uint32_t mwait_hint) * but all Intel CPUs provide hardware coordination. */ - state = (int *)PCPU_PTR(monitorbuf); + state = &PCPU_PTR(monitorbuf)->idle_state; KASSERT(atomic_load_int(state) == STATE_SLEEPING, ("cpu_mwait_cx: wrong monitorbuf state")); atomic_store_int(state, STATE_MWAIT); @@ -422,7 +422,7 @@ cpu_idle_acpi(sbintime_t sbt) { int *state; - state = (int *)PCPU_PTR(monitorbuf); + state = &PCPU_PTR(monitorbuf)->idle_state; atomic_store_int(state, STATE_SLEEPING); /* See comments in cpu_idle_hlt(). */ @@ -441,7 +441,7 @@ cpu_idle_hlt(sbintime_t sbt) { int *state; - state = (int *)PCPU_PTR(monitorbuf); + state = &PCPU_PTR(monitorbuf)->idle_state; atomic_store_int(state, STATE_SLEEPING); /* @@ -473,7 +473,7 @@ cpu_idle_mwait(sbintime_t sbt) { int *state; - state = (int *)PCPU_PTR(monitorbuf); + state = &PCPU_PTR(monitorbuf)->idle_state; atomic_store_int(state, STATE_MWAIT); /* See comments in cpu_idle_hlt(). */ @@ -498,7 +498,7 @@ cpu_idle_spin(sbintime_t sbt) int *state; int i; - state = (int *)PCPU_PTR(monitorbuf); + state = &PCPU_PTR(monitorbuf)->idle_state; atomic_store_int(state, STATE_RUNNING); /* @@ -598,9 +598,11 @@ SYSCTL_INT(_machdep, OID_AUTO, idle_apl31, CTLFLAG_RW, int cpu_idle_wakeup(int cpu) { + struct monitorbuf *mb; int *state; - state = (int *)pcpu_find(cpu)->pc_monitorbuf; + mb = &pcpu_find(cpu)->pc_monitorbuf; + state = &mb->idle_state; switch (atomic_load_int(state)) { case STATE_SLEEPING: return (0);