Date: Tue, 14 Feb 2012 02:01:23 GMT From: Otacílio de Araújo Ramos neto <otacilio.neto@ee.ufcg.edu.br> To: freebsd-gnats-submit@FreeBSD.org Subject: ports/165121: Change-request to port Message-ID: <201202140201.q1E21Nxh095910@red.freebsd.org> Resent-Message-ID: <201202140210.q1E2A6t2033825@freefall.freebsd.org>
next in thread | raw e-mail | index | archive | help
>Number: 165121
>Category: ports
>Synopsis: Change-request to port
>Confidential: no
>Severity: non-critical
>Priority: low
>Responsible: freebsd-ports-bugs
>State: open
>Quarter:
>Keywords:
>Date-Required:
>Class: change-request
>Submitter-Id: current-users
>Arrival-Date: Tue Feb 14 02:10:06 UTC 2012
>Closed-Date:
>Last-Modified:
>Originator: Otacílio de Araújo Ramos neto
>Release: 8.2
>Organization:
>Environment:
FreeBSD squitch 8.2-RELEASE-p2 FreeBSD 8.2-RELEASE-p2 #9: Fri Jul 22 12:30:57 BRT 2011 ota@squitch:/usr/obj/usr/src/sys/SQUITCH i386
>Description:
Building point for Verilog support in the Perl language
>How-To-Repeat:
>Fix:
===> Generating patch
===> Viewing diff with more
diff -ruN --exclude=CVS /usr/ports//cad/p5-Verilog-Perl/Makefile /usr/home/ota/Desktop/p5-Verilog-Perl/Makefile
--- /usr/ports//cad/p5-Verilog-Perl/Makefile 2010-01-17 21:57:34.000000000 -0300
+++ /usr/home/ota/Desktop/p5-Verilog-Perl/Makefile 2012-02-13 22:11:56.000000000 -0300
@@ -2,14 +2,15 @@
# Date created: 11 Apr 2009
# Whom: Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
#
-# $FreeBSD: ports/cad/p5-Verilog-Perl/Makefile,v 1.9 2010/01/18 00:57:34 pgollucci Exp $
+# $FreeBSD: ports/cad/p5-Verilog-Perl/Makefile,v 1.10 2010/07/23 14:33:24 sylvio Exp $
#
PORTNAME= Verilog-Perl
-PORTVERSION= 3.223
+PORTVERSION= 3.313
CATEGORIES= cad perl5
MASTER_SITES= CPAN
PKGNAMEPREFIX= p5-
+#EXTRACT_SUFX= .tgz
MAINTAINER= otacilio.neto@ee.ufcg.edu.br
COMMENT= Building point for Verilog support in the Perl language
@@ -28,9 +29,9 @@
Verilog::Parser.3 Verilog::Getopt.3 Verilog::Netlist::Module.3 \
Verilog::Preproc.3 Verilog::Language.3 Verilog::Netlist::Net.3 \
Verilog::SigParser.3 Verilog::Netlist.3 Verilog::Netlist::Pin.3 \
- Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 \
+ Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 Verilog::Netlist::Defparam.3 \
Verilog::Netlist::File.3 Verilog::Netlist::Subclass.3 \
- Verilog::Netlist::ContAssign.3 \
+ Verilog::Netlist::ContAssign.3 Verilog::Netlist::ModPort.3 \
Verilog::Verilog-Perl.3 Verilog::Netlist::Interface.3 Verilog::Std.3
.include <bsd.port.pre.mk>
diff -ruN --exclude=CVS /usr/ports//cad/p5-Verilog-Perl/distinfo /usr/home/ota/Desktop/p5-Verilog-Perl/distinfo
--- /usr/ports//cad/p5-Verilog-Perl/distinfo 2010-01-17 21:57:34.000000000 -0300
+++ /usr/home/ota/Desktop/p5-Verilog-Perl/distinfo 2012-02-13 22:17:28.000000000 -0300
@@ -1,3 +1,2 @@
-MD5 (Verilog-Perl-3.223.tar.gz) = 54405173d5796dc8dee6a630ae1583c2
-SHA256 (Verilog-Perl-3.223.tar.gz) = 9dc9a42938173580c8cbf5bb46760de53d950f3d2f44ceb3c4d6cad787443df6
-SIZE (Verilog-Perl-3.223.tar.gz) = 212651
+SHA256 (Verilog-Perl-3.313.tar.gz) = d184649d041db2cd506a9629c56537cecba187585e26a11900872b7036ff695e
+SIZE (Verilog-Perl-3.313.tar.gz) = 541181
diff -ruN --exclude=CVS /usr/ports//cad/p5-Verilog-Perl/p5-Verilog-Perl/Makefile /usr/home/ota/Desktop/p5-Verilog-Perl/p5-Verilog-Perl/Makefile
--- /usr/ports//cad/p5-Verilog-Perl/p5-Verilog-Perl/Makefile 2012-02-13 22:05:54.000000000 -0300
+++ /usr/home/ota/Desktop/p5-Verilog-Perl/p5-Verilog-Perl/Makefile 1969-12-31 21:00:00.000000000 -0300
@@ -1,53 +0,0 @@
-# New ports collection makefile for: Verilog-Perl
-# Date created: 11 Apr 2009
-# Whom: Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
-#
-# $FreeBSD: ports/cad/p5-Verilog-Perl/Makefile,v 1.10 2010/07/23 14:33:24 sylvio Exp $
-#
-
-PORTNAME= Verilog-Perl
-PORTVERSION= 3.251
-CATEGORIES= cad perl5
-MASTER_SITES= CPAN
-PKGNAMEPREFIX= p5-
-
-MAINTAINER= otacilio.neto@ee.ufcg.edu.br
-COMMENT= Building point for Verilog support in the Perl language
-
-BUILD_DEPENDS= flex>=2.5.35:${PORTSDIR}/textproc/flex
-
-USE_GMAKE= yes
-USE_PERL5= yes
-USE_BISON= build
-
-PERL_CONFIGURE= yes
-
-MAN1= vhier.1 vpassert.1 vppreproc.1 vrename.1
-
-MAN3= Verilog::EditFiles.3 Verilog::Netlist::Logger.3 \
- Verilog::Parser.3 Verilog::Getopt.3 Verilog::Netlist::Module.3 \
- Verilog::Preproc.3 Verilog::Language.3 Verilog::Netlist::Net.3 \
- Verilog::SigParser.3 Verilog::Netlist.3 Verilog::Netlist::Pin.3 \
- Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 Verilog::Netlist::Defparam.3 \
- Verilog::Netlist::File.3 Verilog::Netlist::Subclass.3 \
- Verilog::Netlist::ContAssign.3 Verilog::Netlist::ModPort.3 \
- Verilog::Verilog-Perl.3 Verilog::Netlist::Interface.3 Verilog::Std.3
-
-.include <bsd.port.pre.mk>
-
-post-patch:
- @${REINPLACE_CMD} -e '/EXE_FILES/ s/ vsplitmodule//' \
- ${WRKSRC}/Makefile.PL
-
-post-configure:
-.if ${OSVERSION} < 700042
- @${REINPLACE_CMD} -e 's|-O2|-O|g' ${WRKSRC}/Makefile
-.endif
-
-post-build:
- cd ${WRKSRC} && make test
-
-test:
- make post-build
-
-.include <bsd.port.post.mk>
diff -ruN --exclude=CVS /usr/ports//cad/p5-Verilog-Perl/p5-Verilog-Perl/distinfo /usr/home/ota/Desktop/p5-Verilog-Perl/p5-Verilog-Perl/distinfo
--- /usr/ports//cad/p5-Verilog-Perl/p5-Verilog-Perl/distinfo 2012-02-13 22:05:54.000000000 -0300
+++ /usr/home/ota/Desktop/p5-Verilog-Perl/p5-Verilog-Perl/distinfo 1969-12-31 21:00:00.000000000 -0300
@@ -1,2 +0,0 @@
-SHA256 (Verilog-Perl-3.251.tar.gz) = ee4742c36f84a6170340a1c79b5e5ebaa230d2fb08f85edde479dfd56cd0b708
-SIZE (Verilog-Perl-3.251.tar.gz) = 232475
diff -ruN --exclude=CVS /usr/ports//cad/p5-Verilog-Perl/p5-Verilog-Perl/pkg-descr /usr/home/ota/Desktop/p5-Verilog-Perl/p5-Verilog-Perl/pkg-descr
--- /usr/ports//cad/p5-Verilog-Perl/p5-Verilog-Perl/pkg-descr 2012-02-13 22:05:54.000000000 -0300
+++ /usr/home/ota/Desktop/p5-Verilog-Perl/p5-Verilog-Perl/pkg-descr 1969-12-31 21:00:00.000000000 -0300
@@ -1,19 +0,0 @@
-The Verilog-Perl library is a building point for Verilog support in the Perl
-language. It includes:
-* Verilog::Getopt which parses command line options similar to C++ and VCS.
-* Verilog::Language which knows the language keywords and parses numbers.
-* Verilog::Netlist which builds netlists out of Verilog files. This allows
- easy scripts to determine things such as the hierarchy of modules.
-* Verilog::Parser invokes callbacks for language tokens.
-* Verilog::Preproc preprocesses the language, and allows reading
- post-processed files right from Perl without temporary files.
-* vpassert inserts PLIish warnings and assertions for any simulator.
-* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
-* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
- cross references and makes it easy to rename signal and module names across
- multiple files. Vrename uses a simple and efficient three step process.
- First, you run vrename to create a list of signals in the design. You then
- edit this list, changing as many symbols as you wish. Vrename is then run a
- second time to apply the changes.
-
-WWW: http://www.veripool.org/wiki/verilog-perl
diff -ruN --exclude=CVS /usr/ports//cad/p5-Verilog-Perl/p5-Verilog-Perl/pkg-plist /usr/home/ota/Desktop/p5-Verilog-Perl/p5-Verilog-Perl/pkg-plist
--- /usr/ports//cad/p5-Verilog-Perl/p5-Verilog-Perl/pkg-plist 2012-02-13 22:05:54.000000000 -0300
+++ /usr/home/ota/Desktop/p5-Verilog-Perl/p5-Verilog-Perl/pkg-plist 1969-12-31 21:00:00.000000000 -0300
@@ -1,36 +0,0 @@
-bin/vhier
-bin/vpassert
-bin/vppreproc
-bin/vrename
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/EditFiles.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Getopt.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Language.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Cell.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ContAssign.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Defparam.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/File.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Interface.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Logger.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ModPort.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Module.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Net.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Pin.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Port.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Subclass.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Parser.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Preproc.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/SigParser.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Std.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Verilog-Perl.pod
-%%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Language/.packlist
-%%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Parser/Parser.bs
-%%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Parser/Parser.so
-%%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Preproc/Preproc.bs
-%%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Preproc/Preproc.so
-@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Preproc
-@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Parser
-@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Language
-@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog
-@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist
-@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/Verilog
diff -ruN --exclude=CVS /usr/ports//cad/p5-Verilog-Perl/pkg-plist /usr/home/ota/Desktop/p5-Verilog-Perl/pkg-plist
--- /usr/ports//cad/p5-Verilog-Perl/pkg-plist 2009-11-04 12:43:10.000000000 -0300
+++ /usr/home/ota/Desktop/p5-Verilog-Perl/pkg-plist 2010-07-23 11:33:24.000000000 -0300
@@ -7,15 +7,17 @@
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Language.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Cell.pm
+%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ContAssign.pm
+%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Defparam.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/File.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Interface.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Logger.pm
+%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ModPort.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Module.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Net.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Pin.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Port.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Subclass.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ContAssign.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Parser.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Preproc.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/SigParser.pm
===> Done
Patch attached with submission follows:
===> Generating patch
===> Viewing diff with more
diff -ruN --exclude=CVS /usr/ports//cad/p5-Verilog-Perl/Makefile /usr/home/ota/Desktop/p5-Verilog-Perl/Makefile
--- /usr/ports//cad/p5-Verilog-Perl/Makefile 2010-01-17 21:57:34.000000000 -0300
+++ /usr/home/ota/Desktop/p5-Verilog-Perl/Makefile 2012-02-13 22:11:56.000000000 -0300
@@ -2,14 +2,15 @@
# Date created: 11 Apr 2009
# Whom: Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
#
-# $FreeBSD: ports/cad/p5-Verilog-Perl/Makefile,v 1.9 2010/01/18 00:57:34 pgollucci Exp $
+# $FreeBSD: ports/cad/p5-Verilog-Perl/Makefile,v 1.10 2010/07/23 14:33:24 sylvio Exp $
#
PORTNAME= Verilog-Perl
-PORTVERSION= 3.223
+PORTVERSION= 3.313
CATEGORIES= cad perl5
MASTER_SITES= CPAN
PKGNAMEPREFIX= p5-
+#EXTRACT_SUFX= .tgz
MAINTAINER= otacilio.neto@ee.ufcg.edu.br
COMMENT= Building point for Verilog support in the Perl language
@@ -28,9 +29,9 @@
Verilog::Parser.3 Verilog::Getopt.3 Verilog::Netlist::Module.3 \
Verilog::Preproc.3 Verilog::Language.3 Verilog::Netlist::Net.3 \
Verilog::SigParser.3 Verilog::Netlist.3 Verilog::Netlist::Pin.3 \
- Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 \
+ Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 Verilog::Netlist::Defparam.3 \
Verilog::Netlist::File.3 Verilog::Netlist::Subclass.3 \
- Verilog::Netlist::ContAssign.3 \
+ Verilog::Netlist::ContAssign.3 Verilog::Netlist::ModPort.3 \
Verilog::Verilog-Perl.3 Verilog::Netlist::Interface.3 Verilog::Std.3
.include <bsd.port.pre.mk>
diff -ruN --exclude=CVS /usr/ports//cad/p5-Verilog-Perl/distinfo /usr/home/ota/Desktop/p5-Verilog-Perl/distinfo
--- /usr/ports//cad/p5-Verilog-Perl/distinfo 2010-01-17 21:57:34.000000000 -0300
+++ /usr/home/ota/Desktop/p5-Verilog-Perl/distinfo 2012-02-13 22:17:28.000000000 -0300
@@ -1,3 +1,2 @@
-MD5 (Verilog-Perl-3.223.tar.gz) = 54405173d5796dc8dee6a630ae1583c2
-SHA256 (Verilog-Perl-3.223.tar.gz) = 9dc9a42938173580c8cbf5bb46760de53d950f3d2f44ceb3c4d6cad787443df6
-SIZE (Verilog-Perl-3.223.tar.gz) = 212651
+SHA256 (Verilog-Perl-3.313.tar.gz) = d184649d041db2cd506a9629c56537cecba187585e26a11900872b7036ff695e
+SIZE (Verilog-Perl-3.313.tar.gz) = 541181
diff -ruN --exclude=CVS /usr/ports//cad/p5-Verilog-Perl/p5-Verilog-Perl/Makefile /usr/home/ota/Desktop/p5-Verilog-Perl/p5-Verilog-Perl/Makefile
--- /usr/ports//cad/p5-Verilog-Perl/p5-Verilog-Perl/Makefile 2012-02-13 22:05:54.000000000 -0300
+++ /usr/home/ota/Desktop/p5-Verilog-Perl/p5-Verilog-Perl/Makefile 1969-12-31 21:00:00.000000000 -0300
@@ -1,53 +0,0 @@
-# New ports collection makefile for: Verilog-Perl
-# Date created: 11 Apr 2009
-# Whom: Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
-#
-# $FreeBSD: ports/cad/p5-Verilog-Perl/Makefile,v 1.10 2010/07/23 14:33:24 sylvio Exp $
-#
-
-PORTNAME= Verilog-Perl
-PORTVERSION= 3.251
-CATEGORIES= cad perl5
-MASTER_SITES= CPAN
-PKGNAMEPREFIX= p5-
-
-MAINTAINER= otacilio.neto@ee.ufcg.edu.br
-COMMENT= Building point for Verilog support in the Perl language
-
-BUILD_DEPENDS= flex>=2.5.35:${PORTSDIR}/textproc/flex
-
-USE_GMAKE= yes
-USE_PERL5= yes
-USE_BISON= build
-
-PERL_CONFIGURE= yes
-
-MAN1= vhier.1 vpassert.1 vppreproc.1 vrename.1
-
-MAN3= Verilog::EditFiles.3 Verilog::Netlist::Logger.3 \
- Verilog::Parser.3 Verilog::Getopt.3 Verilog::Netlist::Module.3 \
- Verilog::Preproc.3 Verilog::Language.3 Verilog::Netlist::Net.3 \
- Verilog::SigParser.3 Verilog::Netlist.3 Verilog::Netlist::Pin.3 \
- Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 Verilog::Netlist::Defparam.3 \
- Verilog::Netlist::File.3 Verilog::Netlist::Subclass.3 \
- Verilog::Netlist::ContAssign.3 Verilog::Netlist::ModPort.3 \
- Verilog::Verilog-Perl.3 Verilog::Netlist::Interface.3 Verilog::Std.3
-
-.include <bsd.port.pre.mk>
-
-post-patch:
- @${REINPLACE_CMD} -e '/EXE_FILES/ s/ vsplitmodule//' \
- ${WRKSRC}/Makefile.PL
-
-post-configure:
-.if ${OSVERSION} < 700042
- @${REINPLACE_CMD} -e 's|-O2|-O|g' ${WRKSRC}/Makefile
-.endif
-
-post-build:
- cd ${WRKSRC} && make test
-
-test:
- make post-build
-
-.include <bsd.port.post.mk>
diff -ruN --exclude=CVS /usr/ports//cad/p5-Verilog-Perl/p5-Verilog-Perl/distinfo /usr/home/ota/Desktop/p5-Verilog-Perl/p5-Verilog-Perl/distinfo
--- /usr/ports//cad/p5-Verilog-Perl/p5-Verilog-Perl/distinfo 2012-02-13 22:05:54.000000000 -0300
+++ /usr/home/ota/Desktop/p5-Verilog-Perl/p5-Verilog-Perl/distinfo 1969-12-31 21:00:00.000000000 -0300
@@ -1,2 +0,0 @@
-SHA256 (Verilog-Perl-3.251.tar.gz) = ee4742c36f84a6170340a1c79b5e5ebaa230d2fb08f85edde479dfd56cd0b708
-SIZE (Verilog-Perl-3.251.tar.gz) = 232475
diff -ruN --exclude=CVS /usr/ports//cad/p5-Verilog-Perl/p5-Verilog-Perl/pkg-descr /usr/home/ota/Desktop/p5-Verilog-Perl/p5-Verilog-Perl/pkg-descr
--- /usr/ports//cad/p5-Verilog-Perl/p5-Verilog-Perl/pkg-descr 2012-02-13 22:05:54.000000000 -0300
+++ /usr/home/ota/Desktop/p5-Verilog-Perl/p5-Verilog-Perl/pkg-descr 1969-12-31 21:00:00.000000000 -0300
@@ -1,19 +0,0 @@
-The Verilog-Perl library is a building point for Verilog support in the Perl
-language. It includes:
-* Verilog::Getopt which parses command line options similar to C++ and VCS.
-* Verilog::Language which knows the language keywords and parses numbers.
-* Verilog::Netlist which builds netlists out of Verilog files. This allows
- easy scripts to determine things such as the hierarchy of modules.
-* Verilog::Parser invokes callbacks for language tokens.
-* Verilog::Preproc preprocesses the language, and allows reading
- post-processed files right from Perl without temporary files.
-* vpassert inserts PLIish warnings and assertions for any simulator.
-* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
-* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
- cross references and makes it easy to rename signal and module names across
- multiple files. Vrename uses a simple and efficient three step process.
- First, you run vrename to create a list of signals in the design. You then
- edit this list, changing as many symbols as you wish. Vrename is then run a
- second time to apply the changes.
-
-WWW: http://www.veripool.org/wiki/verilog-perl
diff -ruN --exclude=CVS /usr/ports//cad/p5-Verilog-Perl/p5-Verilog-Perl/pkg-plist /usr/home/ota/Desktop/p5-Verilog-Perl/p5-Verilog-Perl/pkg-plist
--- /usr/ports//cad/p5-Verilog-Perl/p5-Verilog-Perl/pkg-plist 2012-02-13 22:05:54.000000000 -0300
+++ /usr/home/ota/Desktop/p5-Verilog-Perl/p5-Verilog-Perl/pkg-plist 1969-12-31 21:00:00.000000000 -0300
@@ -1,36 +0,0 @@
-bin/vhier
-bin/vpassert
-bin/vppreproc
-bin/vrename
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/EditFiles.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Getopt.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Language.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Cell.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ContAssign.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Defparam.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/File.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Interface.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Logger.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ModPort.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Module.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Net.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Pin.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Port.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Subclass.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Parser.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Preproc.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/SigParser.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Std.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Verilog-Perl.pod
-%%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Language/.packlist
-%%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Parser/Parser.bs
-%%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Parser/Parser.so
-%%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Preproc/Preproc.bs
-%%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Preproc/Preproc.so
-@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Preproc
-@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Parser
-@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog/Language
-@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/auto/Verilog
-@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist
-@dirrm %%SITE_PERL%%/%%PERL_ARCH%%/Verilog
diff -ruN --exclude=CVS /usr/ports//cad/p5-Verilog-Perl/pkg-plist /usr/home/ota/Desktop/p5-Verilog-Perl/pkg-plist
--- /usr/ports//cad/p5-Verilog-Perl/pkg-plist 2009-11-04 12:43:10.000000000 -0300
+++ /usr/home/ota/Desktop/p5-Verilog-Perl/pkg-plist 2010-07-23 11:33:24.000000000 -0300
@@ -7,15 +7,17 @@
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Language.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Cell.pm
+%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ContAssign.pm
+%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Defparam.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/File.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Interface.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Logger.pm
+%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ModPort.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Module.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Net.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Pin.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Port.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Subclass.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ContAssign.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Parser.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Preproc.pm
%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/SigParser.pm
===> Done
>Release-Note:
>Audit-Trail:
>Unformatted:
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201202140201.q1E21Nxh095910>