Date: Thu, 19 Apr 2012 03:26:21 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r234450 - in head/sys/dev/ath: . ath_hal/ar5210 ath_hal/ar5211 ath_hal/ar5212 ath_hal/ar5312 ath_hal/ar5416 Message-ID: <201204190326.q3J3QLIV063135@svn.freebsd.org>
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Author: adrian Date: Thu Apr 19 03:26:21 2012 New Revision: 234450 URL: http://svn.freebsd.org/changeset/base/234450 Log: Stop using the hardware register value byte order swapping for now, at least until I can root cause what's going on. The only platform I've seen this on is the AR9220 when attached to the AR71xx CPUs. I get immediate PCIe bus errors and all subsequent accesses cause further MIPS bus exceptions. I don't have any other big-endian platforms to test this on. If I get a chance (or two), I'll try to whack this on a bus analyser and see exactly what happens. I'd rather leave this on, especially for slower, embedded platforms. But the #ifdef hell is something I'm trying to avoid. Modified: head/sys/dev/ath/ah_osdep.c head/sys/dev/ath/ah_osdep.h head/sys/dev/ath/ath_hal/ar5210/ar5210_reset.c head/sys/dev/ath/ath_hal/ar5211/ar5211_reset.c head/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c head/sys/dev/ath/ath_hal/ar5312/ar5312_reset.c head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Modified: head/sys/dev/ath/ah_osdep.c ============================================================================== --- head/sys/dev/ath/ah_osdep.c Thu Apr 19 03:20:13 2012 (r234449) +++ head/sys/dev/ath/ah_osdep.c Thu Apr 19 03:26:21 2012 (r234450) @@ -267,12 +267,7 @@ ath_hal_reg_write(struct ath_hal *ah, u_ } if (ah->ah_config.ah_serialise_reg_war) mtx_lock_spin(&ah_regser_mtx); -#if _BYTE_ORDER == _BIG_ENDIAN - if (OS_REG_UNSWAPPED(reg)) - bus_space_write_4(tag, h, reg, val); - else -#endif - bus_space_write_stream_4(tag, h, reg, val); + bus_space_write_4(tag, h, reg, val); if (ah->ah_config.ah_serialise_reg_war) mtx_unlock_spin(&ah_regser_mtx); } @@ -286,12 +281,7 @@ ath_hal_reg_read(struct ath_hal *ah, u_i if (ah->ah_config.ah_serialise_reg_war) mtx_lock_spin(&ah_regser_mtx); -#if _BYTE_ORDER == _BIG_ENDIAN - if (OS_REG_UNSWAPPED(reg)) - val = bus_space_read_4(tag, h, reg); - else -#endif - val = bus_space_read_stream_4(tag, h, reg); + val = bus_space_read_4(tag, h, reg); if (ah->ah_config.ah_serialise_reg_war) mtx_unlock_spin(&ah_regser_mtx); if (ath_hal_alq) { @@ -343,12 +333,7 @@ ath_hal_reg_write(struct ath_hal *ah, u_ if (ah->ah_config.ah_serialise_reg_war) mtx_lock_spin(&ah_regser_mtx); -#if _BYTE_ORDER == _BIG_ENDIAN - if (OS_REG_UNSWAPPED(reg)) - bus_space_write_4(tag, h, reg, val); - else -#endif - bus_space_write_stream_4(tag, h, reg, val); + bus_space_write_4(tag, h, reg, val); if (ah->ah_config.ah_serialise_reg_war) mtx_unlock_spin(&ah_regser_mtx); } @@ -362,12 +347,7 @@ ath_hal_reg_read(struct ath_hal *ah, u_i if (ah->ah_config.ah_serialise_reg_war) mtx_lock_spin(&ah_regser_mtx); -#if _BYTE_ORDER == _BIG_ENDIAN - if (OS_REG_UNSWAPPED(reg)) - val = bus_space_read_4(tag, h, reg); - else -#endif - val = bus_space_read_stream_4(tag, h, reg); + val = bus_space_read_4(tag, h, reg); if (ah->ah_config.ah_serialise_reg_war) mtx_unlock_spin(&ah_regser_mtx); return val; Modified: head/sys/dev/ath/ah_osdep.h ============================================================================== --- head/sys/dev/ath/ah_osdep.h Thu Apr 19 03:20:13 2012 (r234449) +++ head/sys/dev/ath/ah_osdep.h Thu Apr 19 03:26:21 2012 (r234450) @@ -97,39 +97,13 @@ struct ath_hal; extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val); extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg); #else -/* - * The hardware registers are native little-endian byte order. - * Big-endian hosts are handled by enabling hardware byte-swap - * of register reads and writes at reset. But the PCI clock - * domain registers are not byte swapped! Thus, on big-endian - * platforms we have to explicitly byte-swap those registers. - * Most of this code is collapsed at compile time because the - * register values are constants. - */ -#if _BYTE_ORDER == _BIG_ENDIAN -#define OS_REG_WRITE(_ah, _reg, _val) do { \ - if (OS_REG_UNSWAPPED(_reg)) \ - bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \ - (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \ - else \ - bus_space_write_stream_4((bus_space_tag_t)(_ah)->ah_st, \ - (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \ -} while (0) -#define OS_REG_READ(_ah, _reg) \ - (OS_REG_UNSWAPPED(_reg) ? \ - bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \ - (bus_space_handle_t)(_ah)->ah_sh, (_reg)) : \ - bus_space_read_stream_4((bus_space_tag_t)(_ah)->ah_st, \ - (bus_space_handle_t)(_ah)->ah_sh, (_reg))) -#else /* _BYTE_ORDER == _LITTLE_ENDIAN */ #define OS_REG_WRITE(_ah, _reg, _val) \ bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \ (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)) #define OS_REG_READ(_ah, _reg) \ bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \ (bus_space_handle_t)(_ah)->ah_sh, (_reg)) -#endif /* _BYTE_ORDER */ -#endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */ +#endif #ifdef AH_DEBUG_ALQ extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value); Modified: head/sys/dev/ath/ath_hal/ar5210/ar5210_reset.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5210/ar5210_reset.c Thu Apr 19 03:20:13 2012 (r234449) +++ head/sys/dev/ath/ath_hal/ar5210/ar5210_reset.c Thu Apr 19 03:26:21 2012 (r234450) @@ -594,12 +594,10 @@ ar5210SetResetReg(struct ath_hal *ah, ui if ((resetMask & AR_RC_RMAC) == 0) { if (isBigEndian()) { /* - * Set CFG, little-endian for register - * and descriptor accesses. + * Set CFG, little-endian for descriptor accesses. */ - mask = INIT_CONFIG_STATUS | - AR_CFG_SWTD | AR_CFG_SWRD | AR_CFG_SWRG; - OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask)); + mask = INIT_CONFIG_STATUS | AR_CFG_SWTD | AR_CFG_SWRD; + OS_REG_WRITE(ah, AR_CFG, mask); } else OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); } Modified: head/sys/dev/ath/ath_hal/ar5211/ar5211_reset.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5211/ar5211_reset.c Thu Apr 19 03:20:13 2012 (r234449) +++ head/sys/dev/ath/ath_hal/ar5211/ar5211_reset.c Thu Apr 19 03:26:21 2012 (r234450) @@ -764,12 +764,10 @@ ar5211SetResetReg(struct ath_hal *ah, ui if ((resetMask & AR_RC_MAC) == 0) { if (isBigEndian()) { /* - * Set CFG, little-endian for register - * and descriptor accesses. + * Set CFG, little-endian for descriptor accesses. */ - mask = INIT_CONFIG_STATUS | - AR_CFG_SWTD | AR_CFG_SWRD | AR_CFG_SWRG; - OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask)); + mask = INIT_CONFIG_STATUS | AR_CFG_SWTD | AR_CFG_SWRD; + OS_REG_WRITE(ah, AR_CFG, mask); } else OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); } Modified: head/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c Thu Apr 19 03:20:13 2012 (r234449) +++ head/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c Thu Apr 19 03:26:21 2012 (r234450) @@ -1273,14 +1273,13 @@ ar5212SetResetReg(struct ath_hal *ah, ui if ((resetMask & AR_RC_MAC) == 0) { if (isBigEndian()) { /* - * Set CFG, little-endian for register - * and descriptor accesses. + * Set CFG, little-endian for descriptor accesses. */ - mask = INIT_CONFIG_STATUS | AR_CFG_SWRD | AR_CFG_SWRG; + mask = INIT_CONFIG_STATUS | AR_CFG_SWRD; #ifndef AH_NEED_DESC_SWAP mask |= AR_CFG_SWTD; #endif - OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask)); + OS_REG_WRITE(ah, AR_CFG, mask); } else OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); if (ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) Modified: head/sys/dev/ath/ath_hal/ar5312/ar5312_reset.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5312/ar5312_reset.c Thu Apr 19 03:20:13 2012 (r234449) +++ head/sys/dev/ath/ath_hal/ar5312/ar5312_reset.c Thu Apr 19 03:26:21 2012 (r234450) @@ -740,8 +740,7 @@ ar5312SetResetReg(struct ath_hal *ah, ui if ((resetMask & AR_RC_MAC) == 0) { if (isBigEndian()) { /* - * Set CFG, little-endian for register - * and descriptor accesses. + * Set CFG, little-endian for descriptor accesses. */ #ifdef AH_NEED_DESC_SWAP mask = INIT_CONFIG_STATUS | AR_CFG_SWRD; Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Thu Apr 19 03:20:13 2012 (r234449) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Thu Apr 19 03:26:21 2012 (r234450) @@ -1387,16 +1387,15 @@ ar5416SetReset(struct ath_hal *ah, int t if (type == HAL_RESET_COLD) { if (isBigEndian()) { /* - * Set CFG, little-endian for register - * and descriptor accesses. + * Set CFG, little-endian for descriptor accesses. */ - mask = INIT_CONFIG_STATUS | AR_CFG_SWRD | AR_CFG_SWRG; + mask = INIT_CONFIG_STATUS | AR_CFG_SWRD; #ifndef AH_NEED_DESC_SWAP mask |= AR_CFG_SWTD; #endif HALDEBUG(ah, HAL_DEBUG_RESET, "%s Applying descriptor swap\n", __func__); - OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask)); + OS_REG_WRITE(ah, AR_CFG, mask); } else OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); }
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