Date: Tue, 26 Feb 2019 17:20:03 +0000 (UTC) From: Emmanuel Vadot <manu@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r344590 - head/sys/arm64/rockchip/clk Message-ID: <201902261720.x1QHK37x045105@repo.freebsd.org>
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Author: manu Date: Tue Feb 26 17:20:03 2019 New Revision: 344590 URL: https://svnweb.freebsd.org/changeset/base/344590 Log: arm64: rockchip: rk3399_pll: Fix copy paste RK3399 PLLs don't have mode_reg, use the correct register. MFC after: 1 week Modified: head/sys/arm64/rockchip/clk/rk_clk_pll.c Modified: head/sys/arm64/rockchip/clk/rk_clk_pll.c ============================================================================== --- head/sys/arm64/rockchip/clk/rk_clk_pll.c Tue Feb 26 17:08:51 2019 (r344589) +++ head/sys/arm64/rockchip/clk/rk_clk_pll.c Tue Feb 26 17:20:03 2019 (r344590) @@ -427,7 +427,7 @@ rk3399_clk_pll_set_freq(struct clknode *clk, uint64_t /* Setting to slow mode during frequency change */ reg = RK3399_CLK_PLL_MODE_SLOW << RK3399_CLK_PLL_MODE_SHIFT; reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT; - WRITE4(clk, sc->mode_reg, reg); + WRITE4(clk, sc->base_offset + 0xC, reg); /* Setting fbdiv */ READ4(clk, sc->base_offset, ®);
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