Date: Mon, 3 Jun 2019 23:17:35 +0000 (UTC) From: John Baldwin <jhb@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r348592 - head/usr.sbin/bhyve Message-ID: <201906032317.x53NHZxF023676@repo.freebsd.org>
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Author: jhb Date: Mon Jun 3 23:17:35 2019 New Revision: 348592 URL: https://svnweb.freebsd.org/changeset/base/348592 Log: Emulate the AMD MSR_LS_CFG MSR used for various Ryzen errata. Writes are ignored and reads always return zero. Submitted by: José Albornoz <jojo@eljojo.net> (write-only version) Reviewed by: Patrick Mooney, cem MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D19506 Modified: head/usr.sbin/bhyve/xmsr.c Modified: head/usr.sbin/bhyve/xmsr.c ============================================================================== --- head/usr.sbin/bhyve/xmsr.c Mon Jun 3 23:07:46 2019 (r348591) +++ head/usr.sbin/bhyve/xmsr.c Mon Jun 3 23:17:35 2019 (r348592) @@ -72,6 +72,7 @@ emulate_wrmsr(struct vmctx *ctx, int vcpu, uint32_t nu return (0); case MSR_NB_CFG1: + case MSR_LS_CFG: case MSR_IC_CFG: return (0); /* Ignore writes */ @@ -141,6 +142,7 @@ emulate_rdmsr(struct vmctx *ctx, int vcpu, uint32_t nu break; case MSR_NB_CFG1: + case MSR_LS_CFG: case MSR_IC_CFG: /* * The reset value is processor family dependent so
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