From owner-svn-src-user@FreeBSD.ORG Thu Apr 15 19:18:36 2010 Return-Path: Delivered-To: svn-src-user@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 6188C106564A; Thu, 15 Apr 2010 19:18:36 +0000 (UTC) (envelope-from jmallett@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 5081D8FC0C; Thu, 15 Apr 2010 19:18:36 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o3FJIa0w093422; Thu, 15 Apr 2010 19:18:36 GMT (envelope-from jmallett@svn.freebsd.org) Received: (from jmallett@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o3FJIa2l093417; Thu, 15 Apr 2010 19:18:36 GMT (envelope-from jmallett@svn.freebsd.org) Message-Id: <201004151918.o3FJIa2l093417@svn.freebsd.org> From: Juli Mallett Date: Thu, 15 Apr 2010 19:18:36 +0000 (UTC) To: src-committers@freebsd.org, svn-src-user@freebsd.org X-SVN-Group: user MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r206676 - in user/jmallett/octeon/sys/mips/cavium: . dev/rgmii X-BeenThere: svn-src-user@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the experimental " user" src tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Apr 2010 19:18:36 -0000 Author: jmallett Date: Thu Apr 15 19:18:35 2010 New Revision: 206676 URL: http://svn.freebsd.org/changeset/base/206676 Log: o) Rename OCTEON_SMP to SMP. o) Use PCPU_GET(cpuid) rather than unimplemented Octeon method. Do keep the cpuid in ebase just in case. Modified: user/jmallett/octeon/sys/mips/cavium/dev/rgmii/octeon_rgmx.c user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c user/jmallett/octeon/sys/mips/cavium/octeon_mp.c user/jmallett/octeon/sys/mips/cavium/octeon_pcmap_regs.h Modified: user/jmallett/octeon/sys/mips/cavium/dev/rgmii/octeon_rgmx.c ============================================================================== --- user/jmallett/octeon/sys/mips/cavium/dev/rgmii/octeon_rgmx.c Thu Apr 15 19:15:05 2010 (r206675) +++ user/jmallett/octeon/sys/mips/cavium/dev/rgmii/octeon_rgmx.c Thu Apr 15 19:18:35 2010 (r206676) @@ -1481,7 +1481,7 @@ static void octeon_config_hw_units_post_ oct_write64(OCTEON_POW_WORKQUEUE_INT_THRESHOLD(OCTEON_POW_RX_GROUP_NUM), thr.word64); #endif - ciu_enable_interrupts(OCTEON_CORE_ID, OCTEON_RGMX_CIU_INTX, OCTEON_RGMX_CIU_ENX, + ciu_enable_interrupts(PCPU_GET(cpuid), OCTEON_RGMX_CIU_INTX, OCTEON_RGMX_CIU_ENX, (OCTEON_POW_RX_GROUP_MASK | CIU_GENTIMER_BITS_ENABLE(CIU_GENTIMER_NUM_1)), CIU_MIPS_IP2); Modified: user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c ============================================================================== --- user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c Thu Apr 15 19:15:05 2010 (r206675) +++ user/jmallett/octeon/sys/mips/cavium/octeon_machdep.c Thu Apr 15 19:18:35 2010 (r206676) @@ -501,7 +501,7 @@ void ciu_enable_interrupts(int core_num, #endif ciu_intr_bits |= set_these_interrupt_bits; oct_write64(ciu_intr_reg_addr, ciu_intr_bits); -#ifdef OCTEON_SMP +#ifdef SMP mips_wbflush(); #endif oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */ @@ -613,6 +613,14 @@ platform_start(__register_t a0, __regist #endif platform_counter_freq = octeon_get_clock_rate(); mips_timer_init_params(platform_counter_freq, 0); + +#ifdef SMP + /* + * Clear any pending IPIs and enable the IPI interrupt. + */ + oct_write64(OCTEON_CIU_MBOX_CLRX(0), 0xffffffff); + ciu_enable_interrupts(0, CIU_INT_1, CIU_EN_0, OCTEON_CIU_ENABLE_MBOX_INTR, CIU_MIPS_IP3); +#endif } /* impSTART: This stuff should move back into the Cavium SDK */ Modified: user/jmallett/octeon/sys/mips/cavium/octeon_mp.c ============================================================================== --- user/jmallett/octeon/sys/mips/cavium/octeon_mp.c Thu Apr 15 19:15:05 2010 (r206675) +++ user/jmallett/octeon/sys/mips/cavium/octeon_mp.c Thu Apr 15 19:18:35 2010 (r206676) @@ -43,13 +43,18 @@ unsigned octeon_ap_boot = ~0; void platform_ipi_send(int cpuid) { - panic("%s: not yet implemented.", __func__); + oct_write64(OCTEON_CIU_MBOX_SETX(cpuid), 1); + mips_wbflush(); } void platform_ipi_clear(void) { - panic("%s: not yet implemented.", __func__); + uint64_t action; + + action = oct_read64(OCTEON_CIU_MBOX_CLRX(PCPU_GET(cpuid))); + KASSERT(action == 1, ("unexpected IPIs: %#jx", (uintmax_t)action)); + oct_write64(OCTEON_CIU_MBOX_CLRX(PCPU_GET(cpuid)), action); } int @@ -63,10 +68,18 @@ platform_init_ap(int cpuid) { /* * Set the exception base. - * - * XXX Low bits seem to be used for cpuid? */ - mips_wr_prid1(0x80000000); + mips_wr_prid1(0x80000000 | cpuid); + + /* + * Set up interrupts, clear IPIs and unmask the IPI interrupt. + */ + octeon_ciu_reset(); + + oct_write64(OCTEON_CIU_MBOX_CLRX(cpuid), 0xffffffff); + ciu_enable_interrupts(cpuid, CIU_INT_1, CIU_EN_0, OCTEON_CIU_ENABLE_MBOX_INTR, CIU_MIPS_IP3); + + mips_wbflush(); } int Modified: user/jmallett/octeon/sys/mips/cavium/octeon_pcmap_regs.h ============================================================================== --- user/jmallett/octeon/sys/mips/cavium/octeon_pcmap_regs.h Thu Apr 15 19:15:05 2010 (r206675) +++ user/jmallett/octeon/sys/mips/cavium/octeon_pcmap_regs.h Thu Apr 15 19:18:35 2010 (r206676) @@ -54,14 +54,6 @@ #ifndef LOCORE -/* XXXimp: From Cavium's include/pcpu.h, need to port that over */ -#ifndef OCTEON_SMP -#define OCTEON_CORE_ID 0 -#else -extern struct pcpu *cpuid_to_pcpu[]; -#define OCTEON_CORE_ID (mips_rd_coreid()) -#endif - /* * Utility inlines & macros */