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Mon, 15 Jul 2024 12:37:54 GMT (envelope-from git) Date: Mon, 15 Jul 2024 12:37:54 GMT Message-Id: <202407151237.46FCbslM058659@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Andrew Turner Subject: git: 2b3cf14a5152 - stable/13 - arm64: Decode the ID_AA64MMFR3_EL1 register List-Id: Commits to the stable branches of the FreeBSD src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-branches List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-branches@freebsd.org Sender: owner-dev-commits-src-branches@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/stable/13 X-Git-Reftype: branch X-Git-Commit: 2b3cf14a5152049303bc7d22de954af99324f859 Auto-Submitted: auto-generated The branch stable/13 has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=2b3cf14a5152049303bc7d22de954af99324f859 commit 2b3cf14a5152049303bc7d22de954af99324f859 Author: Andrew Turner AuthorDate: 2023-07-06 13:28:23 +0000 Commit: Andrew Turner CommitDate: 2024-07-15 08:09:50 +0000 arm64: Decode the ID_AA64MMFR3_EL1 register Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D40893 (cherry picked from commit c65679143f82e28b3aa078f16311350c31a33776) --- sys/arm64/arm64/identcpu.c | 39 +++++++++++++++++++++++++++++++++++++++ sys/arm64/include/armreg.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c index 60c40c84f965..2750f400fb66 100644 --- a/sys/arm64/arm64/identcpu.c +++ b/sys/arm64/arm64/identcpu.c @@ -129,6 +129,7 @@ struct cpu_desc { uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; uint64_t id_aa64mmfr2; + uint64_t id_aa64mmfr3; uint64_t id_aa64pfr0; uint64_t id_aa64pfr1; uint64_t id_aa64zfr0; @@ -1211,6 +1212,37 @@ static const struct mrs_field id_aa64mmfr2_fields[] = { }; +/* ID_AA64MMFR2_EL1 */ +static const struct mrs_field_value id_aa64mmfr3_spec_fpacc[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, Spec_FPACC, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64mmfr3_mec[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, MEC, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64mmfr3_sctlrx[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, SCTLRX, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field_value id_aa64mmfr3_tcrx[] = { + MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, TCRX, NONE, IMPL), + MRS_FIELD_VALUE_END, +}; + +static const struct mrs_field id_aa64mmfr3_fields[] = { + MRS_FIELD(ID_AA64MMFR3, Spec_FPACC, false, MRS_EXACT, + id_aa64mmfr3_spec_fpacc), + MRS_FIELD(ID_AA64MMFR3, MEC, false, MRS_EXACT, id_aa64mmfr3_mec), + MRS_FIELD(ID_AA64MMFR3, SCTLRX, false, MRS_EXACT, id_aa64mmfr3_sctlrx), + MRS_FIELD(ID_AA64MMFR3, TCRX, false, MRS_EXACT, id_aa64mmfr3_tcrx), + MRS_FIELD_END, +}; + + /* ID_AA64PFR0_EL1 */ static const struct mrs_field_value id_aa64pfr0_csv3[] = { MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_NONE, ""), @@ -1747,6 +1779,7 @@ static const struct mrs_user_reg user_regs[] = { USER_REG(ID_AA64MMFR0_EL1, id_aa64mmfr0), USER_REG(ID_AA64MMFR1_EL1, id_aa64mmfr1), USER_REG(ID_AA64MMFR2_EL1, id_aa64mmfr2), + USER_REG(ID_AA64MMFR3_EL1, id_aa64mmfr3), USER_REG(ID_AA64PFR0_EL1, id_aa64pfr0), USER_REG(ID_AA64PFR1_EL1, id_aa64pfr1), @@ -2443,6 +2476,11 @@ print_cpu_features(u_int cpu) print_id_register(sb, "Memory Model Features 2", cpu_desc[cpu].id_aa64mmfr2, id_aa64mmfr2_fields); + /* AArch64 Memory Model Feature Register 3 */ + if (SHOULD_PRINT_REG(id_aa64mmfr3)) + print_id_register(sb, "Memory Model Features 3", + cpu_desc[cpu].id_aa64mmfr3, id_aa64mmfr3_fields); + /* AArch64 Debug Feature Register 0 */ if (SHOULD_PRINT_REG(id_aa64dfr0)) print_id_register(sb, "Debug Features 0", @@ -2555,6 +2593,7 @@ identify_cpu(u_int cpu) cpu_desc[cpu].id_aa64mmfr0 = READ_SPECIALREG(id_aa64mmfr0_el1); cpu_desc[cpu].id_aa64mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1); cpu_desc[cpu].id_aa64mmfr2 = READ_SPECIALREG(id_aa64mmfr2_el1); + cpu_desc[cpu].id_aa64mmfr3 = READ_SPECIALREG(id_aa64mmfr3_el1); cpu_desc[cpu].id_aa64pfr0 = READ_SPECIALREG(id_aa64pfr0_el1); cpu_desc[cpu].id_aa64pfr1 = READ_SPECIALREG(id_aa64pfr1_el1); diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 098c55361913..1a5863b82535 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -1088,6 +1088,34 @@ #define ID_AA64MMFR2_E0PD_NONE (UL(0x0) << ID_AA64MMFR2_E0PD_SHIFT) #define ID_AA64MMFR2_E0PD_IMPL (UL(0x1) << ID_AA64MMFR2_E0PD_SHIFT) +/* ID_AA64MMFR3_EL1 */ +#define ID_AA64MMFR3_EL1 MRS_REG(ID_AA64MMFR3_EL1) +#define ID_AA64MMFR3_EL1_op0 3 +#define ID_AA64MMFR3_EL1_op1 0 +#define ID_AA64MMFR3_EL1_CRn 0 +#define ID_AA64MMFR3_EL1_CRm 7 +#define ID_AA64MMFR3_EL1_op2 3 +#define ID_AA64MMFR3_TCRX_SHIFT 0 +#define ID_AA64MMFR3_TCRX_MASK (UL(0xf) << ID_AA64MMFR3_TCRX_SHIFT) +#define ID_AA64MMFR3_TCRX_VAL(x) ((x) & ID_AA64MMFR3_TCRX_MASK) +#define ID_AA64MMFR3_TCRX_NONE (UL(0x0) << ID_AA64MMFR3_TCRX_SHIFT) +#define ID_AA64MMFR3_TCRX_IMPL (UL(0x1) << ID_AA64MMFR3_TCRX_SHIFT) +#define ID_AA64MMFR3_SCTLRX_SHIFT 4 +#define ID_AA64MMFR3_SCTLRX_MASK (UL(0xf) << ID_AA64MMFR3_SCTLRX_SHIFT) +#define ID_AA64MMFR3_SCTLRX_VAL(x) ((x) & ID_AA64MMFR3_SCTLRX_MASK) +#define ID_AA64MMFR3_SCTLRX_NONE (UL(0x0) << ID_AA64MMFR3_SCTLRX_SHIFT) +#define ID_AA64MMFR3_SCTLRX_IMPL (UL(0x1) << ID_AA64MMFR3_SCTLRX_SHIFT) +#define ID_AA64MMFR3_MEC_SHIFT 28 +#define ID_AA64MMFR3_MEC_MASK (UL(0xf) << ID_AA64MMFR3_MEC_SHIFT) +#define ID_AA64MMFR3_MEC_VAL(x) ((x) & ID_AA64MMFR3_MEC_MASK) +#define ID_AA64MMFR3_MEC_NONE (UL(0x0) << ID_AA64MMFR3_MEC_SHIFT) +#define ID_AA64MMFR3_MEC_IMPL (UL(0x1) << ID_AA64MMFR3_MEC_SHIFT) +#define ID_AA64MMFR3_Spec_FPACC_SHIFT 60 +#define ID_AA64MMFR3_Spec_FPACC_MASK (UL(0xf) << ID_AA64MMFR3_Spec_FPACC_SHIFT) +#define ID_AA64MMFR3_Spec_FPACC_VAL(x) ((x) & ID_AA64MMFR3_Spec_FPACC_MASK) +#define ID_AA64MMFR3_Spec_FPACC_NONE (UL(0x0) << ID_AA64MMFR3_Spec_FPACC_SHIFT) +#define ID_AA64MMFR3_Spec_FPACC_IMPL (UL(0x1) << ID_AA64MMFR3_Spec_FPACC_SHIFT) + /* ID_AA64PFR0_EL1 */ #define ID_AA64PFR0_EL1 MRS_REG(ID_AA64PFR0_EL1) #define ID_AA64PFR0_EL1_op0 3