From owner-freebsd-hackers@FreeBSD.ORG Sun Dec 30 06:14:36 2007 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 6C30316A419; Sun, 30 Dec 2007 06:14:36 +0000 (UTC) (envelope-from perryh@pluto.rain.com) Received: from agora.rdrop.com (agora.rdrop.com [199.26.172.34]) by mx1.freebsd.org (Postfix) with ESMTP id 4D14713C442; Sun, 30 Dec 2007 06:14:36 +0000 (UTC) (envelope-from perryh@pluto.rain.com) Received: from agora.rdrop.com (66@localhost [127.0.0.1]) by agora.rdrop.com (8.13.1/8.12.7) with ESMTP id lBU6EZUN029989 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Sat, 29 Dec 2007 22:14:35 -0800 (PST) (envelope-from perryh@pluto.rain.com) Received: (from uucp@localhost) by agora.rdrop.com (8.13.1/8.12.9/Submit) with UUCP id lBU6EZ64029988; Sat, 29 Dec 2007 22:14:35 -0800 (PST) Received: from fbsd61 by pluto.rain.com (4.1/SMI-4.1-pluto-M2060407) id AA22826; Sat, 29 Dec 07 22:11:13 PST Date: Sat, 29 Dec 2007 22:09:44 -0800 From: perryh@pluto.rain.com To: ivoras@freebsd.org Message-Id: <47773628.CaSnQ8XhoTY1UQz3%perryh@pluto.rain.com> References: <20071229.122221.-432830441.imp@bsdimp.com> <4776d1d7.zI7kRv9uFoaBNKnQ%perryh@pluto.rain.com> In-Reply-To: User-Agent: nail 11.25 7/29/05 Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Cc: freebsd-hackers@freebsd.org Subject: Re: Architectures with strict alignment? X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 30 Dec 2007 06:14:36 -0000 Ivan Voras wrote: > perryh@pluto.rain.com wrote: > > > The degree to which a PowerPC imposes a strict alignment > > requirement depends on both the particular processor model > > and the operation being performed. > > > > For ordinary integer arithmetic and logical operations, newer > > PPC processors tend to be more tolerant (although misalignment > > will typically carry a performance penalty) ... > > How would it behave in operations like > > x = x + 1 > > where x is unaligned in memory? A RISC would have to load the > value from memory, increment it and store it. It depends on the processor type. IIRC most of the recent ones (7xx, 74xx) will handle it in hardware, taking a few extra cycles to do the extra memory accesses. Some of the older ones (403) will take an alignment exception, which can potentially be fixed up by a handler but at a cost of, at least, hundreds of cycles -- and only if the OS or the application has provided the handler. I recently ran into a case where a PPC970 took an alignment exception on something resembling this, but I think it was because the data cache was disabled (the 970's hardware misalignment handler being part of the cache logic).