From owner-freebsd-mips@FreeBSD.ORG Wed Mar 28 08:40:40 2012 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id A5291106566B; Wed, 28 Mar 2012 08:40:40 +0000 (UTC) (envelope-from ray@dlink.ua) Received: from smtp.dlink.ua (smtp.dlink.ua [193.138.187.146]) by mx1.freebsd.org (Postfix) with ESMTP id 601B38FC14; Wed, 28 Mar 2012 08:40:39 +0000 (UTC) Received: from terran.dlink.ua (unknown [192.168.10.90]) (Authenticated sender: ray) by smtp.dlink.ua (Postfix) with ESMTPSA id 4949BC493A; Wed, 28 Mar 2012 11:31:30 +0300 (EEST) Date: Wed, 28 Mar 2012 11:32:18 +0300 From: Aleksandr Rybalko To: Adrian Chadd Message-Id: <20120328113218.e93fe3c5.ray@dlink.ua> In-Reply-To: References: Organization: D-Link X-Mailer: Sylpheed 2.7.1 (GTK+ 2.20.1; i386-portbld-freebsd8.0) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: freebsd-mips@freebsd.org Subject: Re: [patch] enable mdio port 1, remove phy mask hard coding X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Mar 2012 08:40:40 -0000 On Tue, 27 Mar 2012 22:44:54 -0700 Adrian Chadd wrote: >> Hi all, >> >> This patch does a few things: >> >> * it adds mdio port 1 (from MAC1/arge1); >> * it removes the hard-coded assumption that arge0/arge1 share the >> same mdio bus, which I believe is only relevant for AR71xx; >> * it removes phymask from the arge config; >> * it introduces a new configuration parameter, "multiphy", which >> binds the port to the fake phy. The existing code does this if >> phymask has >> >1 bit set. This makes it absolutely obvious. >> >> Since ar724x CPUs have >1 MDIO bus, we have to do this work to >> support the switch phys that ship with these things. >> >> >> This now raises the issue of how to handle switch PHYs and normal >> PHYs on alternate busses. For example, the PB47 reference board has >> the PHY for arge1 hang off the only MDIO bus on the board (AR7161) - >> which is MDIO 0. >> >> It's about time we fixed this stuff. I want to push in the switch >> code from juli/pat/ray/stb now. >> >> >> adrian Patch looks good to me, but I don't understand: why you use sc->arge_mac_unit as argument to ARGE_MII_READ/ARGE_MII_WRITE, but not assigned bus_space_tag and bus_space_handle? If you make ARGE_MII_READ/ARGE_MII_WRITE as alias to ARGE_READ/ARGE_WRITE, maybe with offset to MDIO regs, it will be more clear. Thanks. WBW -- Alexandr Rybalko aka Alex RAY