From owner-svn-src-all@freebsd.org Tue Mar 13 18:14:49 2018 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 09731F3D33A; Tue, 13 Mar 2018 18:14:49 +0000 (UTC) (envelope-from chmeeedalf@gmail.com) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G2" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 70C986CE18; Tue, 13 Mar 2018 18:14:48 +0000 (UTC) (envelope-from chmeeedalf@gmail.com) Received: by mail-lf0-x241.google.com with SMTP id h127-v6so782432lfg.12; Tue, 13 Mar 2018 11:14:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=PD8VmU2ZCXijd5lFeUz1daQ3FR/UF1CRBXqF91NInKM=; b=nLp9zGQnUxByZXDqGiaxOSWgyXaO9/ROB55ryrf4QrrlR8x/riQqmKEJ9Eg9SaT0FU wWxEf6g/KKj74+SD0pRnLr+gdQ+nUYLv4d7J8WHuW0OhxFIy5Qy5wKkWEASZ8MnHIOzE lnKkZEQJ5UuLvU4COdl4NYPg/ARQmXUw7vKTVbqH5AUxIyntaji1OwQkGiJvK/x53LIj 6yCDqtYhu/XH/AlvFZVRTT8ezEaihIQ6Zhqek+Ozyuryw+Huv4UqTX8YKRKULN/XdUga iGCVtfqNATRpNMOu2S5rCSawYk04Qg3OgsmjhWDGrjDZesUSrhqyAr631Rdsq3Ie04/U 6vyQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alumni-cwru-edu.20150623.gappssmtp.com; s=20150623; h=mime-version:sender:in-reply-to:references:from:date:message-id :subject:to:cc; bh=PD8VmU2ZCXijd5lFeUz1daQ3FR/UF1CRBXqF91NInKM=; b=hk3opffCQPbul+em68j5Z9+zSankSlWCkJmwb5LWxONcopqYGcVDlNnt6/NZYZ4M6U JXbjpxatOnR+J16Ap5tA9oeE2qKKKFBvYffNPj5pZUr76Txq9AregOt44e5siI3shEnh onSRKR5GBId94bTI6/EgP8wU7AFH1cWZDzIzzO6IfkwxzyIY9v8NGs6Ne1NgZqegfH1u FcSndnXCWm/x5c007l5Nh+5+0dAiXVtSDZD9DN+uVC9GvY+2V+btJYhrDeq2yRjSxhxl nGhTNdT3y6kKH5E1dIUbizIOjeBAtjB1zie/dQ5upe3QkIl1HeLzPPxs2OwOLOGwzb+U t4zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:sender:in-reply-to:references:from :date:message-id:subject:to:cc; bh=PD8VmU2ZCXijd5lFeUz1daQ3FR/UF1CRBXqF91NInKM=; b=ESCOyF68RuM1tOf4F7OEXfcux6MvTF28uBQOb+T3sdOCrzAI5iU6Xctg5SltE03+je 5NFGbf21TDZVx4uFJzJzI6JTrtygoITtupvkbcdpo3A8EtB0ofkoF/FO5Hc1pJfUNQ+r go4Iz9na7wEQjj8EDZmkZV269s5TP3+HydNMV0WzyyrW4DULzKC9PPA9N+n5DHvzhxI7 /Bi0zQh2iiKUdm0DBdXq0/I1yrJJmIG219mCodh4kS2nub0+Az0c1HrnxbSM9rvtGbIK AnWYgWqjqYqrQOi4BuHrWzXBF5Tzg1uBv/S2wPthcOhI3B/iK857QhWtjR0C+II2YIL1 sa9A== X-Gm-Message-State: AElRT7HJxE/drmmqVqskMMDSIt7bU3Wc78dvQUxanjv9EX35E8SiCiI+ kkvGWWpRKFhkgL/S9OnjdIj76sahJA+7uF8j/Bk= X-Google-Smtp-Source: AG47ELtm+Xq4/MET5x3HiqOmQhHu4yRs+yVYwT8Dcm/3FJlG9/ZeV48WjVNwzDngxI1RE4+qmGjqUAnoj9qckJX4Djo= X-Received: by 2002:a19:114f:: with SMTP id g76-v6mr1287157lfi.0.1520964886720; Tue, 13 Mar 2018 11:14:46 -0700 (PDT) MIME-Version: 1.0 Sender: chmeeedalf@gmail.com Received: by 10.46.85.26 with HTTP; Tue, 13 Mar 2018 11:14:46 -0700 (PDT) In-Reply-To: <201803131503.w2DF3wLJ064986@repo.freebsd.org> References: <201803131503.w2DF3wLJ064986@repo.freebsd.org> From: Justin Hibbits Date: Tue, 13 Mar 2018 13:14:46 -0500 X-Google-Sender-Auth: UfgJL8f4Ze_y_i3_SbQ014EETA0 Message-ID: Subject: Re: svn commit: r330845 - in head/sys/powerpc: aim ofw powerpc To: Nathan Whitehorn Cc: src-committers , svn-src-all@freebsd.org, svn-src-head@freebsd.org Content-Type: text/plain; charset="UTF-8" X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 13 Mar 2018 18:14:49 -0000 This broke the powerpc (32-bit) build. On Tue, Mar 13, 2018 at 10:03 AM, Nathan Whitehorn wrote: > Author: nwhitehorn > Date: Tue Mar 13 15:03:58 2018 > New Revision: 330845 > URL: https://svnweb.freebsd.org/changeset/base/330845 > > Log: > Execute PowerPC64/AIM kernel from direct map region when possible. > > When the kernel can be in real mode in early boot, we can execute from > high addresses aliased to the kernel's physical memory. If that high > address has the first two bits set to 1 (0xc...), those addresses will > automatically become part of the direct map. This reduces page table > pressure from the kernel and it sets up the kernel to be used with > radix translation, for which it has to be up here. > > This is accomplished by exploiting the fact that all PowerPC kernels are > built as position-independent executables and relocate themselves > on start. Before this patch, the kernel runs at 1:1 VA:PA, but that > VA/PA is random and set by the bootloader. Very early, it processes > its ELF relocations to operate wherever it happens to find itself. > This patch uses that mechanism to re-enter and re-relocate the kernel > a second time witha new base address set up in the early parts of > powerpc_init(). > > Reviewed by: jhibbits > Differential Revision: D14647 > > Modified: > head/sys/powerpc/aim/aim_machdep.c > head/sys/powerpc/aim/locore64.S > head/sys/powerpc/aim/mmu_oea64.c > head/sys/powerpc/ofw/ofwcall64.S > head/sys/powerpc/powerpc/machdep.c > > Modified: head/sys/powerpc/aim/aim_machdep.c > ============================================================================== > --- head/sys/powerpc/aim/aim_machdep.c Tue Mar 13 15:02:46 2018 (r330844) > +++ head/sys/powerpc/aim/aim_machdep.c Tue Mar 13 15:03:58 2018 (r330845) > @@ -160,15 +160,72 @@ extern void *dlmisstrap, *dlmisssize; > extern void *dsmisstrap, *dsmisssize; > > extern void *ap_pcpu; > +extern void __restartkernel(vm_offset_t, vm_offset_t, vm_offset_t, void *, uint32_t, register_t offset, register_t msr); > > +void aim_early_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, > + void *mdp, uint32_t mdp_cookie); > void aim_cpu_init(vm_offset_t toc); > > void > +aim_early_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp, > + uint32_t mdp_cookie) > +{ > + register_t scratch; > + > + /* > + * If running from an FDT, make sure we are in real mode to avoid > + * tromping on firmware page tables. Everything in the kernel assumes > + * 1:1 mappings out of firmware, so this won't break anything not > + * already broken. This doesn't work if there is live OF, since OF > + * may internally use non-1:1 mappings. > + */ > + if (ofentry == 0) > + mtmsr(mfmsr() & ~(PSL_IR | PSL_DR)); > + > +#ifdef __powerpc64__ > + /* > + * If in real mode, relocate to high memory so that the kernel > + * can execute from the direct map. > + */ > + if (!(mfmsr() & PSL_DR) && > + (vm_offset_t)&aim_early_init < DMAP_BASE_ADDRESS) > + __restartkernel(fdt, 0, ofentry, mdp, mdp_cookie, > + DMAP_BASE_ADDRESS, mfmsr()); > +#endif > + > + /* Various very early CPU fix ups */ > + switch (mfpvr() >> 16) { > + /* > + * PowerPC 970 CPUs have a misfeature requested by Apple that > + * makes them pretend they have a 32-byte cacheline. Turn this > + * off before we measure the cacheline size. > + */ > + case IBM970: > + case IBM970FX: > + case IBM970MP: > + case IBM970GX: > + scratch = mfspr(SPR_HID5); > + scratch &= ~HID5_970_DCBZ_SIZE_HI; > + mtspr(SPR_HID5, scratch); > + break; > + #ifdef __powerpc64__ > + case IBMPOWER7: > + case IBMPOWER7PLUS: > + case IBMPOWER8: > + case IBMPOWER8E: > + /* XXX: get from ibm,slb-size in device tree */ > + n_slbs = 32; > + break; > + #endif > + } > +} > + > +void > aim_cpu_init(vm_offset_t toc) > { > size_t trap_offset, trapsize; > vm_offset_t trap; > - register_t msr, scratch; > + register_t msr; scratch is used in powerpc, but not powerpc64.