Date: Tue, 18 Jul 2000 23:09:56 +0200 (CEST) From: =?ISO-8859-1?Q?G=E9rard_Roudier?= <groudier@club-internet.fr> To: "Justin T. Gibbs" <gibbs@plutotech.com> Cc: mjacob@feral.com, "Justin T. Gibbs" <gibbs@FreeBSD.org>, cvs-committers@FreeBSD.org, cvs-all@FreeBSD.org Subject: Re: cvs commit: src/sys/cam cam_ccb.h cam_xpt.c src/sys/cam/scsi scsi_all.c scsi_message.h src/sys/dev/aic7xxx aicasm_insformat.h 93cx6.c 93cx6.h ahc_eisa.c ahc_pci.c aic7xxx.c aic7xxx.h aic7xxx.reg aic7xxx.seq aicasm.c aicasm.h aicasm_gram.y ... Message-ID: <Pine.LNX.4.10.10007182242190.1928-100000@linux.local> In-Reply-To: <200007182025.OAA53788@pluto.plutotech.com>
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First, thanks for your commit. I will look into and steal any good idea=20 from you I will found. :-) On Tue, 18 Jul 2000, Justin T. Gibbs wrote: > >Whew! > > > >What's the '39 bit addressing'? >=20 > In the past, the S/G format looked like: >=20 > uint8_t=09=09address[4]; > uint8_t=09=09datalen[3]; > uint8_t=09=09spare; >=20 > Through some firmware manipulation, that last byte, other than a flag > bit, can be used as the 5th byte of the address. >=20 > >Also- maybe it's time to start considering 64 bit PCI >=20 > I'm hoping that being able to address 512GB will be enough > for a while. I'd rather not expand the size of the S/G list > members for address space no-one will be touching for the > foreseeable future. This does not seem so simple. Most systems I read about that allow 64 bit addressing from the PCI BUS=20 require some high address bits beyond bit 39 to be set in the address=20 for the bridge to understand 64 bit DMA adressing. Note that the SYMBIOS 53C8XX 64 bit PCI chips support a 40 bit PCI adressing for table-indirect MOVEs but donnot provide any way to set high address bits, thus they do have this problem. I mailed a SYMBIOS ingenieer a couple of years ago about and suggest them to add some register for setting the higher bits, but they probably were too much focusing on current technology and preferently Intel. The SYMBIOS chips also support a MOVE64 instructions (3DWORDS) that can work on paper for full 64 bit addressing. But this requires to dynamically builds SCRIPTS in memory and have to deal with the complexity of tampering segment registers. In fact these chips have: - A 8 bit ALU - 32 bit addressing - 32 bit segments to tamper for building 64 bit addresses. Hmmm... Intel PAE Painful Address Extension seems simple compared to=20 32 bit PCI chips extended to 64 bit PCI addressing. Anyway, the most interesting feature of 64 bit PCI is the doubling of=20 the BUS bandwidth that is required for PCI to support new needs for=20 BUS bandwidth. G=E9rard. To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe cvs-all" in the body of the message
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