Date: Sun, 23 Feb 2014 18:59:47 +0000 (UTC) From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r262382 - in projects/arm64/sys/arm64: arm64 include Message-ID: <201402231859.s1NIxltD077567@svn.freebsd.org>
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Author: andrew Date: Sun Feb 23 18:59:47 2014 New Revision: 262382 URL: http://svnweb.freebsd.org/changeset/base/262382 Log: Get the kernel to the point it is running from the virtual address space Added: projects/arm64/sys/arm64/include/asm.h (contents, props changed) Modified: projects/arm64/sys/arm64/arm64/locore.S projects/arm64/sys/arm64/include/pte.h Modified: projects/arm64/sys/arm64/arm64/locore.S ============================================================================== --- projects/arm64/sys/arm64/arm64/locore.S Sun Feb 23 18:57:50 2014 (r262381) +++ projects/arm64/sys/arm64/arm64/locore.S Sun Feb 23 18:59:47 2014 (r262382) @@ -27,6 +27,7 @@ */ #include "assym.s" +#include <machine/asm.h> #include <machine/armreg.h> #include <machine/hypervisor.h> #include <machine/param.h> @@ -68,15 +69,23 @@ _start: /* Enable the mmu */ bl start_mmu + ldr x29, .Lvirtdone + br x29 + +virtdone: /* Load the address of the fvp UART */ mov x0, 0x1c090000 - /* Load 'A' */ - mov x1, 0x41 - /* Print 'A' */ + /* Load 'B' */ + mov x1, 0x42 + /* Print 'B' */ str x1, [x0] 1: b 1b + .align 3 +.Lvirtdone: + .quad virtdone + /* * If we are started in EL2, configure the required hypervisor * registers and drop to EL1. @@ -118,7 +127,7 @@ drop_to_el1: mov x2, #(PSR_F | PSR_I | PSR_A | PSR_D | PSR_M_EL1h) msr spsr_el2, x2 - /* Set the address to return to */ + /* Set the address to return to our return address */ msr elr_el2, x30 eret @@ -153,9 +162,6 @@ hyp_vectors: VECT_EMPTY /* FIQ 32-bit EL1 */ VECT_EMPTY /* Error 32-bit EL1 */ -hyp_trap_invalid: - b hyp_trap_invalid - /* * Get the delta between the physical address we were loaded to and the * virtual address we expect to run from. This is used when building the @@ -213,6 +219,26 @@ create_pagetables: b.lo 1b /* + * Build the TTBR1 maps. + */ + + /* Create the kernel space L2 table */ + mov x6, x26 + mov x7, #1 + mov x8, #(KERNBASE & L2_BLOCK_MASK) + mov x9, x28 + bl build_block_pagetable + + /* Move to the l1 table */ + add x26, x26, #1, lsl #PAGE_SHIFT + + /* Link the l1 -> l2 table */ + mov x9, x6 + mov x6, x26 + bl link_l1_pagetable + + + /* * Build the TTBR0 maps. */ add x27, x26, #1, lsl #PAGE_SHIFT @@ -272,13 +298,58 @@ build_section_pagetable: * * x6 = L1 table * x8 = Virtual Address - * x9 = L2 PA + * x9 = L2 PA (trashed) * x11, x12 and x13 are trashed */ link_l1_pagetable: /* * Link an L1 -> L2 table entry. */ + /* Find the table index */ + lsr x11, x8, #L1_SHIFT + and x11, x11, #Ln_ADDR_MASK + + /* Build the L1 block entry */ + mov x12, #L1_TABLE + + /* Only use the output address bits */ + lsr x9, x9, #12 + orr x12, x12, x9, lsl #12 + + /* Store the entry */ + str x12, [x6, x11, lsl #3] + + ret + +/* + * Builds count 2 MiB page table entry + * x6 = L2 table + * x7 = Type (0 = Device, 1 = Normal) + * x8 = VA start + * x9 = PA start (trashed) + * x10 = Entry count (TODO) + * x11, x12 and x13 are trashed + */ +build_block_pagetable: + /* + * Build the L2 table entry. + */ + /* Find the table index */ + lsr x11, x8, #L2_SHIFT + and x11, x11, #Ln_ADDR_MASK + + /* Build the L2 block entry */ + lsl x12, x7, #2 + orr x12, x12, #L2_BLOCK + orr x12, x12, #(ATTR_AF) + + /* Only use the output address bits */ + lsr x9, x9, #L2_SHIFT + orr x12, x12, x9, lsl #L2_SHIFT + + /* Store the entry */ + str x12, [x6, x11, lsl #3] + ret start_mmu: Added: projects/arm64/sys/arm64/include/asm.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ projects/arm64/sys/arm64/include/asm.h Sun Feb 23 18:59:47 2014 (r262382) @@ -0,0 +1,33 @@ +/*- + * Copyright (c) 2014 Andrew Turner + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef _MACHINE_ASM_H_ +#define _MACHINE_ASM_H_ + +#define UINT64_C(x) (x) + +#endif /* _MACHINE_ASM_H_ */ Modified: projects/arm64/sys/arm64/include/pte.h ============================================================================== --- projects/arm64/sys/arm64/include/pte.h Sun Feb 23 18:57:50 2014 (r262381) +++ projects/arm64/sys/arm64/include/pte.h Sun Feb 23 18:59:47 2014 (r262382) @@ -70,6 +70,8 @@ typedef uint64_t pt_entry_t; /* page ta #define L2_BLOCK L0_BLOCK #define L2_TABLE L0_TABLE +#define L2_BLOCK_MASK UINT64_C(0xffffffe00000) + /* Level 3 table, 4KiB per entry */ #define L3_SHIFT 12 #define L3_INVAL 0x0
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