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Date:      Tue, 3 Jan 2012 00:26:11 +0000 (UTC)
From:      Pyun YongHyeon <yongari@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-7@freebsd.org
Subject:   svn commit: r229356 - stable/7/sys/dev/bge
Message-ID:  <201201030026.q030QBMS096692@svn.freebsd.org>

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Author: yongari
Date: Tue Jan  3 00:26:11 2012
New Revision: 229356
URL: http://svn.freebsd.org/changeset/base/229356

Log:
  MFC r226814-226815,226820-226821,226864,226866-226867:
  r226814:
    Rename definition of BGE_SOFTWARE_GENCOMM_* to more readable ones.
    The origin of GENCOMM seems to come from Alteon Tigon Host/NIC
    interface definition where it defines general communications region
    which is active when firmware is loaded and running.  This region
    was used in communication between the host and processor internal
    to the Tigon chip.
    Broadcom data sheet also defines the region as 'Software Gencomm'
    in NetXtreme memory map but lacks detailed description of its
    interface so it was hard to know which ones are used for which
    interface.
    This change shall slightly enhance readability.
  
    No functional changes.
  
  r226815:
    Define MAC address mail box and use it instead of using
    hard-coded value.
  
  r226820:
    Offset 0x6810 is RX-RISC event register. Rename BGE_CPU_EVENT with
    BGE_RX_CPU_EVENT for readability.
    Additionally define BGE_TX_CPU_EVENT for TX-RSIC event register(BCM570[0-4] only).
  
  r226821:
    SRAM offset 0x0C04 is used by driver to inform the IPMI/ASF firmware
    about the various driver events like load, unload, reset, suspend,
    restart, and ioctl operations.
    Define driver's event rather than using hard-coded values.  We don't
    still send suspend/resume event to firmware.
  
    Previously bge(4) used BGE_SDI_STATUS to send events. Because driver
    has to access firmware mail box to inform current state, using
    BGE_SDI_STATUS register was wrong. The end result was the same as
    BGE_SDI_STATUS is 0x0C04.
  
    No functional changes.
  
  r226864:
    Rename BGE_FW_DRV_ALIVE/BGE_FW_PAUSE to BGE_FW_CMD_DRV_ALIVE/BGE_FW_CMD_PAUSE.
    Also add more firmware commands(not used yet).
    No functional changes.
  
  r226866:
    Rename hard-coded value 1 << 14 with BGE_RX_CPU_DRV_EVENT.
    This bit(SW event 7 in publicly available data sheet) is used to
    make RX CPU handle a firmware command and the bit is automatically
    cleared after RX CPU completed the command.
    Generally firmware command takes the following steps.
     1. Write BGE_SRAM_FW_CMD_MB with a command.
     2. Write BGE_SRAM_FW_CMD_LEN_MB with the length of the command in bytes.
     3. Write BGE_SRAM_FW_CMD_DATA_MB with actual command data.
     4. Generate BGE_RX_CPU_EVENT and let firmware handle the command.
     5. Wait for the ACK of the firmware command.
  
    No functional changes.
  
  r226867:
    Define BGE_FW_HB_TIMEOUT_SEC and remove one more magic value.
    bge(4) sends BGE_FW_CMD_DRV_ALIVE command to firmware every 2
    seconds.  BGE_FW_CMD_DRV_ALIVE command requires 4 bytes data.  This
    data contains timeout value in seconds until the next
    BGE_FW_CMD_DRV_ALIVE command.
    Broadcom recommends driver set the value 3 times longer than the
    interval that it sends BGE_FW_CMD_DRV_ALIVE.  Currently bge(4) uses
    3 seconds so probably we have to increase it in future and use
    different ALIVE command(e.g. BGE_FW_CMD_DRV_ALIVE3).
  
    No functional changes.

Modified:
  stable/7/sys/dev/bge/if_bge.c
  stable/7/sys/dev/bge/if_bgereg.h
Directory Properties:
  stable/7/sys/   (props changed)
  stable/7/sys/cddl/contrib/opensolaris/   (props changed)
  stable/7/sys/contrib/dev/acpica/   (props changed)
  stable/7/sys/contrib/pf/   (props changed)

Modified: stable/7/sys/dev/bge/if_bge.c
==============================================================================
--- stable/7/sys/dev/bge/if_bge.c	Tue Jan  3 00:24:44 2012	(r229355)
+++ stable/7/sys/dev/bge/if_bge.c	Tue Jan  3 00:26:11 2012	(r229356)
@@ -1309,15 +1309,17 @@ bge_sig_pre_reset(struct bge_softc *sc, 
 	 * Some chips don't like this so only do this if ASF is enabled
 	 */
 	if (sc->bge_asf_mode)
-		bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
+		bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
 
 	if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
 		switch (type) {
 		case BGE_RESET_START:
-			bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
+			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
+			    BGE_FW_DRV_STATE_START);
 			break;
 		case BGE_RESET_STOP:
-			bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
+			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
+			    BGE_FW_DRV_STATE_UNLOAD);
 			break;
 		}
 	}
@@ -1330,11 +1332,13 @@ bge_sig_post_reset(struct bge_softc *sc,
 	if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
 		switch (type) {
 		case BGE_RESET_START:
-			bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001);
+			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
+			    BGE_FW_DRV_STATE_START_DONE);
 			/* START DONE */
 			break;
 		case BGE_RESET_STOP:
-			bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002);
+			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
+			    BGE_FW_DRV_STATE_UNLOAD_DONE);
 			break;
 		}
 	}
@@ -1347,10 +1351,12 @@ bge_sig_legacy(struct bge_softc *sc, int
 	if (sc->bge_asf_mode) {
 		switch (type) {
 		case BGE_RESET_START:
-			bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */
+			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
+			    BGE_FW_DRV_STATE_START);
 			break;
 		case BGE_RESET_STOP:
-			bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */
+			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
+			    BGE_FW_DRV_STATE_UNLOAD);
 			break;
 		}
 	}
@@ -1362,12 +1368,13 @@ bge_stop_fw(struct bge_softc *sc)
 	int i;
 
 	if (sc->bge_asf_mode) {
-		bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE);
-		CSR_WRITE_4(sc, BGE_CPU_EVENT,
-		    CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
+		bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
+		CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
+		    CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
 
 		for (i = 0; i < 100; i++ ) {
-			if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14)))
+			if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
+			    BGE_RX_CPU_DRV_EVENT))
 				break;
 			DELAY(10);
 		}
@@ -3081,9 +3088,9 @@ bge_attach(device_t dev)
 	}
 
 	sc->bge_asf_mode = 0;
-	if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG)
-	    == BGE_MAGIC_NUMBER)) {
-		if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG)
+	if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
+	    BGE_SRAM_DATA_SIG_MAGIC)) {
+		if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG)
 		    & BGE_HWCFG_ASF) {
 			sc->bge_asf_mode |= ASF_ENABLE;
 			sc->bge_asf_mode |= ASF_STACKUP;
@@ -3197,8 +3204,8 @@ bge_attach(device_t dev)
 	 * by its PCI subsystem ID, as we do below for the SysKonnect
 	 * SK-9D41.
 	 */
-	if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
-		hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
+	if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
+		hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
 	else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
 	    (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
 		if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
@@ -3433,9 +3440,9 @@ bge_reset(struct bge_softc *sc)
 	/*
 	 * Write the magic number to SRAM at offset 0xB50.
 	 * When firmware finishes its initialization it will
-	 * write ~BGE_MAGIC_NUMBER to the same location.
+	 * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
 	 */
-	bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
+	bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
 
 	reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
 
@@ -3560,8 +3567,8 @@ bge_reset(struct bge_softc *sc)
 		 */
 		for (i = 0; i < BGE_TIMEOUT; i++) {
 			DELAY(10);
-			val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
-			if (val == ~BGE_MAGIC_NUMBER)
+			val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
+			if (val == ~BGE_SRAM_FW_MB_MAGIC)
 				break;
 		}
 
@@ -4096,12 +4103,14 @@ bge_asf_driver_up(struct bge_softc *sc)
 			sc->bge_asf_count --;
 		else {
 			sc->bge_asf_count = 2;
-			bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW,
-			    BGE_FW_DRV_ALIVE);
-			bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4);
-			bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3);
-			CSR_WRITE_4(sc, BGE_CPU_EVENT,
-			    CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14));
+			bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
+			    BGE_FW_CMD_DRV_ALIVE);
+			bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
+			bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
+			    BGE_FW_HB_TIMEOUT_SEC);
+			CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
+			    CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
+			    BGE_RX_CPU_DRV_EVENT);
 		}
 	}
 }
@@ -5934,11 +5943,11 @@ bge_get_eaddr_mem(struct bge_softc *sc, 
 {
 	uint32_t mac_addr;
 
-	mac_addr = bge_readmem_ind(sc, 0x0c14);
+	mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
 	if ((mac_addr >> 16) == 0x484b) {
 		ether_addr[0] = (uint8_t)(mac_addr >> 8);
 		ether_addr[1] = (uint8_t)mac_addr;
-		mac_addr = bge_readmem_ind(sc, 0x0c18);
+		mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
 		ether_addr[2] = (uint8_t)(mac_addr >> 24);
 		ether_addr[3] = (uint8_t)(mac_addr >> 16);
 		ether_addr[4] = (uint8_t)(mac_addr >> 8);

Modified: stable/7/sys/dev/bge/if_bgereg.h
==============================================================================
--- stable/7/sys/dev/bge/if_bgereg.h	Tue Jan  3 00:24:44 2012	(r229355)
+++ stable/7/sys/dev/bge/if_bgereg.h	Tue Jan  3 00:26:11 2012	(r229356)
@@ -71,12 +71,15 @@
 #define	BGE_STATS_BLOCK_END		0x00000AFF
 #define	BGE_STATUS_BLOCK		0x00000B00
 #define	BGE_STATUS_BLOCK_END		0x00000B4F
-#define	BGE_SOFTWARE_GENCOMM		0x00000B50
-#define	BGE_SOFTWARE_GENCOMM_SIG	0x00000B54
-#define	BGE_SOFTWARE_GENCOMM_NICCFG	0x00000B58
-#define	BGE_SOFTWARE_GENCOMM_FW		0x00000B78
-#define	BGE_SOFTWARE_GENNCOMM_FW_LEN	0x00000B7C
-#define	BGE_SOFTWARE_GENNCOMM_FW_DATA	0x00000B80
+#define	BGE_SRAM_FW_MB			0x00000B50
+#define	BGE_SRAM_DATA_SIG		0x00000B54
+#define	BGE_SRAM_DATA_CFG		0x00000B58
+#define	BGE_SRAM_FW_CMD_MB		0x00000B78
+#define	BGE_SRAM_FW_CMD_LEN_MB		0x00000B7C
+#define	BGE_SRAM_FW_CMD_DATA_MB		0x00000B80
+#define	BGE_SRAM_FW_DRV_STATE_MB	0x00000C04
+#define	BGE_SRAM_MAC_ADDR_HIGH_MB	0x00000C14
+#define	BGE_SRAM_MAC_ADDR_LOW_MB	0x00000C18
 #define	BGE_SOFTWARE_GENCOMM_END	0x00000FFF
 #define	BGE_UNMAPPED			0x00001000
 #define	BGE_UNMAPPED_END		0x00001FFF
@@ -87,8 +90,24 @@
 #define	BGE_SEND_RING_1_TO_4_END	0x00005FFF
 
 /* Firmware interface */
-#define	BGE_FW_DRV_ALIVE		0x00000001
-#define	BGE_FW_PAUSE			0x00000002
+#define	BGE_SRAM_DATA_SIG_MAGIC		0x4B657654	/* 'KevT' */
+
+#define	BGE_FW_CMD_DRV_ALIVE		0x00000001
+#define	BGE_FW_CMD_PAUSE		0x00000002
+#define	BGE_FW_CMD_IPV4_ADDR_CHANGE	0x00000003
+#define	BGE_FW_CMD_IPV6_ADDR_CHANGE	0x00000004
+#define	BGE_FW_CMD_LINK_UPDATE		0x0000000C
+#define	BGE_FW_CMD_DRV_ALIVE2		0x0000000D
+#define	BGE_FW_CMD_DRV_ALIVE3		0x0000000E
+
+#define	BGE_FW_HB_TIMEOUT_SEC		3
+
+#define	BGE_FW_DRV_STATE_START		0x00000001
+#define	BGE_FW_DRV_STATE_START_DONE	0x80000001
+#define	BGE_FW_DRV_STATE_UNLOAD		0x00000002
+#define	BGE_FW_DRV_STATE_UNLOAD_DONE	0x80000002
+#define	BGE_FW_DRV_STATE_WOL		0x00000003
+#define	BGE_FW_DRV_STATE_SUSPEND	0x00000004
 
 /* Mappings for internal memory configuration */
 #define	BGE_STD_RX_RINGS		0x00006000
@@ -1875,7 +1894,8 @@
 #define	BGE_MODE_CTL			0x6800
 #define	BGE_MISC_CFG			0x6804
 #define	BGE_MISC_LOCAL_CTL		0x6808
-#define	BGE_CPU_EVENT			0x6810
+#define	BGE_RX_CPU_EVENT		0x6810
+#define	BGE_TX_CPU_EVENT		0x6820
 #define	BGE_EE_ADDR			0x6838
 #define	BGE_EE_DATA			0x683C
 #define	BGE_EE_CTL			0x6840
@@ -1883,6 +1903,8 @@
 #define	BGE_EE_DELAY			0x6848
 #define	BGE_FASTBOOT_PC			0x6894
 
+#define	BGE_RX_CPU_DRV_EVENT		0x00004000
+
 /*
  * NVRAM Control registers
  */
@@ -2052,10 +2074,10 @@
  * This magic number is written to the firmware mailbox at 0xb50
  * before a software reset is issued.  After the internal firmware
  * has completed its initialization it will write the opposite of
- * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the
- * driver to synchronize with the firmware.
+ * this value, ~BGE_SRAM_FW_MB_MAGIC, to the same location,
+ * allowing the driver to synchronize with the firmware.
  */
-#define	BGE_MAGIC_NUMBER                0x4B657654
+#define	BGE_SRAM_FW_MB_MAGIC	0x4B657654
 
 typedef struct {
 	uint32_t		bge_addr_hi;



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