From owner-svn-src-all@FreeBSD.ORG Thu Feb 21 06:18:42 2013 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.FreeBSD.org [8.8.178.115]) by hub.freebsd.org (Postfix) with ESMTP id 6693EC3D; Thu, 21 Feb 2013 06:18:42 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) by mx1.freebsd.org (Postfix) with ESMTP id 49B1B11C8; Thu, 21 Feb 2013 06:18:42 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.5/8.14.5) with ESMTP id r1L6IgwS000793; Thu, 21 Feb 2013 06:18:42 GMT (envelope-from adrian@svn.freebsd.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.5/8.14.5/Submit) id r1L6IfTL000788; Thu, 21 Feb 2013 06:18:41 GMT (envelope-from adrian@svn.freebsd.org) Message-Id: <201302210618.r1L6IfTL000788@svn.freebsd.org> From: Adrian Chadd Date: Thu, 21 Feb 2013 06:18:41 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r247085 - head/sys/dev/ath X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Feb 2013 06:18:42 -0000 Author: adrian Date: Thu Feb 21 06:18:40 2013 New Revision: 247085 URL: http://svnweb.freebsd.org/changeset/base/247085 Log: Add a new option to limit the maximum size of aggregates. The default is to limit them to what the hardware is capable of. Add sysctl twiddles for both the non-RTS and RTS protected aggregate generation. Whilst here, add some comments about stuff that I've discovered during my exploration of the TX aggregate / delimiter setup path from the reference driver. Modified: head/sys/dev/ath/if_ath.c head/sys/dev/ath/if_ath_sysctl.c head/sys/dev/ath/if_ath_tx.h head/sys/dev/ath/if_ath_tx_ht.c head/sys/dev/ath/if_athvar.h Modified: head/sys/dev/ath/if_ath.c ============================================================================== --- head/sys/dev/ath/if_ath.c Thu Feb 21 06:12:26 2013 (r247084) +++ head/sys/dev/ath/if_ath.c Thu Feb 21 06:18:40 2013 (r247085) @@ -799,6 +799,7 @@ ath_attach(u_int16_t devid, struct ath_s sc->sc_hwq_limit = ATH_AGGR_MIN_QDEPTH; sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW; sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH; + sc->sc_aggr_limit = ATH_AGGR_MAXSIZE; /* * Check if the hardware requires PCI register serialisation. Modified: head/sys/dev/ath/if_ath_sysctl.c ============================================================================== --- head/sys/dev/ath/if_ath_sysctl.c Thu Feb 21 06:12:26 2013 (r247084) +++ head/sys/dev/ath/if_ath_sysctl.c Thu Feb 21 06:18:40 2013 (r247085) @@ -704,7 +704,7 @@ ath_sysctlattach(struct ath_softc *sc) SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "hwq_limit", CTLFLAG_RW, &sc->sc_hwq_limit, 0, - ""); + "Hardware queue depth before software-queuing TX frames"); SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tid_hwq_lo", CTLFLAG_RW, &sc->sc_tid_hwq_lo, 0, ""); @@ -712,6 +712,12 @@ ath_sysctlattach(struct ath_softc *sc) "tid_hwq_hi", CTLFLAG_RW, &sc->sc_tid_hwq_hi, 0, ""); + /* Aggregate length twiddles */ + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, + "aggr_limit", CTLFLAG_RW, &sc->sc_aggr_limit, 0, ""); + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, + "rts_aggr_limit", CTLFLAG_RW, &sc->sc_rts_aggr_limit, 0, ""); + SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "txq_data_minfree", CTLFLAG_RW, &sc->sc_txq_data_minfree, 0, "Minimum free buffers before adding a data frame" Modified: head/sys/dev/ath/if_ath_tx.h ============================================================================== --- head/sys/dev/ath/if_ath_tx.h Thu Feb 21 06:12:26 2013 (r247084) +++ head/sys/dev/ath/if_ath_tx.h Thu Feb 21 06:18:40 2013 (r247085) @@ -79,6 +79,11 @@ #define BAW_WITHIN(_start, _bawsz, _seqno) \ ((((_seqno) - (_start)) & 4095) < (_bawsz)) +/* + * Maximum aggregate size + */ +#define ATH_AGGR_MAXSIZE 65530 + extern void ath_freetx(struct mbuf *m); extern void ath_tx_node_flush(struct ath_softc *sc, struct ath_node *an); extern void ath_tx_txq_drain(struct ath_softc *sc, struct ath_txq *txq); Modified: head/sys/dev/ath/if_ath_tx_ht.c ============================================================================== --- head/sys/dev/ath/if_ath_tx_ht.c Thu Feb 21 06:12:26 2013 (r247084) +++ head/sys/dev/ath/if_ath_tx_ht.c Thu Feb 21 06:18:40 2013 (r247085) @@ -346,12 +346,19 @@ ath_compute_num_delims(struct ath_softc * crypto hardware catch up. This could be tuned per-MAC and * per-rate, but for now we'll simply assume encryption is * always enabled. + * + * Also note that the Atheros reference driver inserts two + * delimiters by default for pre-AR9380 peers. This will + * include "that" required delimiter. */ ndelim += ATH_AGGR_ENCRYPTDELIM; /* * For AR9380, there's a minimum number of delimeters * required when doing RTS. + * + * XXX TODO: this is only needed if (a) RTS/CTS is enabled, and + * XXX (b) this is the first sub-frame in the aggregate. */ if (sc->sc_use_ent && (sc->sc_ent_cfg & AH_ENT_RTSCTS_DELIM_WAR) && ndelim < AH_FIRST_DESC_NDELIMS) @@ -420,9 +427,12 @@ ath_compute_num_delims(struct ath_softc static int ath_get_aggr_limit(struct ath_softc *sc, struct ath_buf *bf) { - int amin = 65530; + int amin = ATH_AGGR_MAXSIZE; int i; + if (sc->sc_aggr_limit > 0 && sc->sc_aggr_limit < ATH_AGGR_MAXSIZE) + amin = sc->sc_aggr_limit; + for (i = 0; i < ATH_RC_NUM; i++) { if (bf->bf_state.bfs_rc[i].tries == 0) continue; @@ -488,6 +498,13 @@ ath_rateseries_setup(struct ath_softc *s * XXX It's overridden in the HAL rate scenario function * XXX for now. */ + /* + * XXX TODO: When the NIC is capable of three stream TX, + * transmit 1/2 stream rates on two streams. + * + * This reduces the power consumption of the NIC and + * keeps it within the PCIe slot power limits. + */ series[i].ChSel = sc->sc_txchainmask; if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) Modified: head/sys/dev/ath/if_athvar.h ============================================================================== --- head/sys/dev/ath/if_athvar.h Thu Feb 21 06:12:26 2013 (r247084) +++ head/sys/dev/ath/if_athvar.h Thu Feb 21 06:18:40 2013 (r247085) @@ -718,6 +718,7 @@ struct ath_softc { int sc_txchainmask; /* currently configured TX chainmask */ int sc_rxchainmask; /* currently configured RX chainmask */ int sc_rts_aggr_limit; /* TX limit on RTS aggregates */ + int sc_aggr_limit; /* TX limit on all aggregates */ /* Queue limits */