From owner-svn-src-all@FreeBSD.ORG Tue Jul 13 17:24:31 2010 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 341DD106564A; Tue, 13 Jul 2010 17:24:31 +0000 (UTC) (envelope-from imp@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 227BA8FC0A; Tue, 13 Jul 2010 17:24:31 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o6DHOUXa003730; Tue, 13 Jul 2010 17:24:31 GMT (envelope-from imp@svn.freebsd.org) Received: (from imp@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o6DHOUac003728; Tue, 13 Jul 2010 17:24:30 GMT (envelope-from imp@svn.freebsd.org) Message-Id: <201007131724.o6DHOUac003728@svn.freebsd.org> From: Warner Losh Date: Tue, 13 Jul 2010 17:24:30 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r210009 - head/sys/mips/include X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 13 Jul 2010 17:24:31 -0000 Author: imp Date: Tue Jul 13 17:24:30 2010 New Revision: 210009 URL: http://svn.freebsd.org/changeset/base/210009 Log: Define break value for ddb. Use int32/intptr casts for exception vector names. Define MIPS_SR_INT_MASK again Change MIPS_XKPHYS_CCA_* to MIPS_CCA_* since we can use them in many contexts Minor gratuitous whitespace churn Modified: head/sys/mips/include/cpuregs.h Modified: head/sys/mips/include/cpuregs.h ============================================================================== --- head/sys/mips/include/cpuregs.h Tue Jul 13 17:21:42 2010 (r210008) +++ head/sys/mips/include/cpuregs.h Tue Jul 13 17:24:30 2010 (r210009) @@ -81,7 +81,7 @@ #define MIPS_KSEG0_LARGEST_PHYS (0x20000000) #define MIPS_PHYS_MASK (0x1fffffff) -#if !defined(_LOCORE) +#ifndef LOCORE #define MIPS_KUSEG_START 0x00000000 #define MIPS_KSEG0_START ((intptr_t)(int32_t)0x80000000) #define MIPS_KSEG0_END ((intptr_t)(int32_t)0x9fffffff) @@ -91,9 +91,9 @@ #define MIPS_KSSEG_END ((intptr_t)(int32_t)0xdfffffff) #define MIPS_KSEG3_START ((intptr_t)(int32_t)0xe0000000) #define MIPS_KSEG3_END ((intptr_t)(int32_t)0xffffffff) - #define MIPS_KSEG2_START MIPS_KSSEG_START #define MIPS_KSEG2_END MIPS_KSSEG_END +#endif #define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START) #define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START) @@ -112,15 +112,15 @@ #define MIPS_XKPHYS_START 0x8000000000000000 #define MIPS_XKPHYS_END 0xbfffffffffffffff -#define MIPS_XKPHYS_CCA_UC 0x02 /* Uncached. */ -#define MIPS_XKPHYS_CCA_CNC 0x03 /* Cacheable non-coherent. */ +#define MIPS_CCA_UC 0x02 /* Uncached. */ +#define MIPS_CCA_CNC 0x03 /* Cacheable non-coherent. */ #define MIPS_PHYS_TO_XKPHYS(cca,x) \ ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x)) #define MIPS_PHYS_TO_XKPHYS_CACHED(x) \ - ((0x2ULL << 62) | ((unsigned long long)(MIPS_XKPHYS_CCA_CNC) << 59) | (x)) + ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_CNC) << 59) | (x)) #define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \ - ((0x2ULL << 62) | ((unsigned long long)(MIPS_XKPHYS_CCA_UC) << 59) | (x)) + ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_UC) << 59) | (x)) #define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x07ffffffffffffffULL) @@ -130,8 +130,6 @@ #define MIPS_XKSEG_START 0xc000000000000000 #define MIPS_XKSEG_END 0xc00000ff80000000 -#endif - /* CPU dependent mtc0 hazard hook */ #ifdef TARGET_OCTEON #define COP0_SYNC nop; nop; nop; nop; nop; @@ -197,7 +195,7 @@ #define MIPS_SR_INT_IE 0x00000001 /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ -/*#define MIPS_SR_INT_MASK 0x0000ff00*/ +#define MIPS_SR_INT_MASK 0x0000ff00 /* * The R2000/R3000-specific status register bit definitions. @@ -476,20 +474,20 @@ * * Common vectors: reset and UTLB miss. */ -#define MIPS_RESET_EXC_VEC 0xBFC00000 -#define MIPS_UTLB_MISS_EXC_VEC 0x80000000 +#define MIPS_RESET_EXC_VEC ((intptr_t)(int32_t)0xBFC00000) +#define MIPS_UTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000000) /* * MIPS-1 general exception vector (everything else) */ -#define MIPS1_GEN_EXC_VEC 0x80000080 +#define MIPS1_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000080) /* * MIPS-III exception vectors */ -#define MIPS3_XTLB_MISS_EXC_VEC 0x80000080 -#define MIPS3_CACHE_ERR_EXC_VEC 0x80000100 -#define MIPS3_GEN_EXC_VEC 0x80000180 +#define MIPS3_XTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000080) +#define MIPS3_CACHE_ERR_EXC_VEC ((intptr_t)(int32_t)0x80000100) +#define MIPS3_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000180) /* * TX79 (R5900) exception vectors @@ -643,6 +641,7 @@ #define MIPS_BREAK_SSTEP_VAL 513 #define MIPS_BREAK_BRKPT_VAL 514 #define MIPS_BREAK_SOVER_VAL 515 +#define MIPS_BREAK_DDB_VAL 516 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ @@ -651,6 +650,8 @@ (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) +#define MIPS_BREAK_DDB (MIPS_BREAK_INSTR | \ + (MIPS_BREAK_DDB_VAL << MIPS_BREAK_VAL_SHIFT)) /* * Mininum and maximum cache sizes.