From owner-freebsd-hackers Mon Aug 10 20:39:52 1998 Return-Path: Received: (from majordom@localhost) by hub.freebsd.org (8.8.8/8.8.8) id UAA24741 for freebsd-hackers-outgoing; Mon, 10 Aug 1998 20:39:52 -0700 (PDT) (envelope-from owner-freebsd-hackers@FreeBSD.ORG) Received: from allegro.lemis.com (allegro.lemis.com [192.109.197.134]) by hub.freebsd.org (8.8.8/8.8.8) with ESMTP id UAA24735 for ; Mon, 10 Aug 1998 20:39:49 -0700 (PDT) (envelope-from grog@freebie.lemis.com) Received: from freebie.lemis.com (freebie.lemis.com [192.109.197.137]) by allegro.lemis.com (8.9.1/8.9.0) with ESMTP id NAA12355; Tue, 11 Aug 1998 13:09:13 +0930 (CST) Received: (from grog@localhost) by freebie.lemis.com (8.9.1/8.9.0) id NAA21297; Tue, 11 Aug 1998 13:09:11 +0930 (CST) Message-ID: <19980811130910.Q20188@freebie.lemis.com> Date: Tue, 11 Aug 1998 13:09:10 +0930 From: Greg Lehey To: Patrick McAndrew Cc: John Baldwin , FreeBSD Hackers , John Baldwin , dg@root.com Subject: Re: AMD-specific kernel code (was: How long a wait?) References: <19980810123341.X11095@freebie.lemis.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Mailer: Mutt 0.91.1i In-Reply-To: ; from Patrick McAndrew on Mon, Aug 10, 1998 at 11:33:52PM -0400 WWW-Home-Page: http://www.lemis.com/~grog Organization: LEMIS, PO Box 460, Echunga SA 5153, Australia Phone: +61-8-8388-8286 Fax: +61-8-8388-8725 Mobile: +61-41-739-7062 Sender: owner-freebsd-hackers@FreeBSD.ORG Precedence: bulk X-Loop: FreeBSD.ORG On Monday, 10 August 1998 at 23:33:52 -0400, Patrick McAndrew wrote: > On Mon, 10 Aug 1998, Greg Lehey wrote: > >> On Sunday, 9 August 1998 at 23:00:24 -0400, John Baldwin wrote: >>>>> I just looked at the patch. Other than some KNF style bugs, it seems >>>>> okay. >>>>> I don't have any AMD K5/K6 machines, however, so I can't test it and won't >>>>> be committing it. > > I missed the first part of this thread, is this patch for AMD K6 > processors (does it utilitze their RISC core (or whatever it is))? It's a relatively small patch which enables write allocation. This is a modified way of handling pending writes when the cache line is not in L1 cachec: instead of a normal write cycle, it performs a burst read cycle of 32 bytes into L1 cache, and merges the write data into the cache. This wins when there are lots of local references, and loses when there are not (because reading the cache line takes longer than most writes). > Where can i get info and the patch? Info is in an AMD application note: http://www.amd.com/K6/k6docs/pdf/21326d.pdf. The patches are at ftp://ftp.lemis.com/pub/AMD-write-allocate-patch. > How stable is it? I've been running it for two days. It just sets a processor register according to the documentation, so I don't see much room for instability. The only question is, is it worth it? I found about a 5% degradation in performance when building a world. Others have claimed 15% improvement in web servers. Given the nature of the fix (which has to be enabled via the kernel option CPU_AMD_WT_ALLOC), there's no conflict in that. I'm thinking of finding a way to enable it on the fly. I'd be very interested to hear how other people fare with it. Greg -- See complete headers for address and phone numbers finger grog@lemis.com for PGP public key To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hackers" in the body of the message