Date: Sun, 3 May 1998 16:01:02 -0700 (PDT) From: Matthew Dillon <dillon@backplane.com> To: Poul-Henning Kamp <phk@critter.freebsd.dk> Cc: Nate Williams <nate@mt.sri.com>, freebsd-bugs@FreeBSD.ORG Subject: Re: i386/5398 Message-ID: <199805032301.QAA04963@apollo.backplane.com>
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Well, yes, but if it's a software blit (the only thing that would
actually monopolize the PCI bus that way), it's just a tight code
loop and the worst case interrupt latency is only that which is
required to clear out the pci write pipeline, which is usually less
then a microsecond. If it's a hardware blit, such as you get when
you shift windows around, there's normally no PCI activity whatsoever
and this is also true of most pattern blits since the patterns are
stored in video memory. And, in anycase, the chipsets limit the
burst size the dma master is allowed to do. This sort of thing cannot
account for enough serial latency on its own to overrun the fifo
that badly unless it's being helped a bit by interrupt disablement
inside the kernel somewhere. And most blits aren't 3 or 4 MB of data
anyway unless you are redrawing the whole screen.
-Matt
:
:By monopolizing the PCI bus, while blitting 3 or 4 MB data, I can
:certainly see PCI starvation. Remeber that to blt 3 MB around, you
:have to read 3 MB and write 3MB, so that is 6MB over a 133MB/sec bus,
:giving a minimum duration of 45 msec per blt.
:
:Why do you think BLT is being put into the graphics chip by so many
:people ?
:
:Now, can we stop this futile waste of everybodys time ?
:
:Thankyou!
:
:--
:Poul-Henning Kamp FreeBSD coreteam member
:phk@FreeBSD.ORG "Real hackers run -current on their laptop."
:"ttyv0" -- What UNIX calls a $20K state-of-the-art, 3D, hi-res color terminal
:
Matthew Dillon Engineering, BEST Internet Communications, Inc.
<dillon@backplane.com>
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