From owner-svn-src-head@freebsd.org Wed Jan 10 21:08:45 2018 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 1D183E770BF; Wed, 10 Jan 2018 21:08:45 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id D4F076CA99; Wed, 10 Jan 2018 21:08:44 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 3291A2EA8; Wed, 10 Jan 2018 21:08:44 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w0AL8huN017248; Wed, 10 Jan 2018 21:08:43 GMT (envelope-from jhb@FreeBSD.org) Received: (from jhb@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w0AL8hm8017244; Wed, 10 Jan 2018 21:08:43 GMT (envelope-from jhb@FreeBSD.org) Message-Id: <201801102108.w0AL8hm8017244@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jhb set sender to jhb@FreeBSD.org using -f From: John Baldwin Date: Wed, 10 Jan 2018 21:08:43 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r327790 - head/sys/mips/mips X-SVN-Group: head X-SVN-Commit-Author: jhb X-SVN-Commit-Paths: head/sys/mips/mips X-SVN-Commit-Revision: 327790 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 10 Jan 2018 21:08:45 -0000 Author: jhb Date: Wed Jan 10 21:08:43 2018 New Revision: 327790 URL: https://svnweb.freebsd.org/changeset/base/327790 Log: Set the 'FR' bit in the status register for N32 kernels. This permits N32 hard-float binaries to use 64-bit floating point registers (which is what N32 binaries expect) matching the N64 ABI. Reviewed by: imp, jmallett Sponsored by: DARPA / AFRL Differential Revision: https://reviews.freebsd.org/D13830 Modified: head/sys/mips/mips/exception.S head/sys/mips/mips/locore.S head/sys/mips/mips/swtch.S head/sys/mips/mips/trap.c Modified: head/sys/mips/mips/exception.S ============================================================================== --- head/sys/mips/mips/exception.S Wed Jan 10 21:05:46 2018 (r327789) +++ head/sys/mips/mips/exception.S Wed Jan 10 21:08:43 2018 (r327790) @@ -1110,7 +1110,7 @@ NESTED(MipsFPTrap, CALLFRAME_SIZ, ra) REG_S ra, CALLFRAME_RA(sp) .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ) -#if defined(__mips_n64) +#if defined(__mips_n32) || defined(__mips_n64) or t1, t0, MIPS_SR_COP_1_BIT | MIPS_SR_FR #else or t1, t0, MIPS_SR_COP_1_BIT Modified: head/sys/mips/mips/locore.S ============================================================================== --- head/sys/mips/mips/locore.S Wed Jan 10 21:05:46 2018 (r327789) +++ head/sys/mips/mips/locore.S Wed Jan 10 21:08:43 2018 (r327790) @@ -117,8 +117,11 @@ VECTOR(_locore, unknown) * Enable FPU */ li t1, MIPS_SR_COP_1_BIT +#if defined(__mips_n32) || defined(__mips_n64) + or t1, MIPS_SR_FR +#endif #ifdef __mips_n64 - or t1, MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS_SR_FR + or t1, MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX #endif #endif /* Modified: head/sys/mips/mips/swtch.S ============================================================================== --- head/sys/mips/mips/swtch.S Wed Jan 10 21:05:46 2018 (r327789) +++ head/sys/mips/mips/swtch.S Wed Jan 10 21:08:43 2018 (r327790) @@ -416,7 +416,7 @@ LEAF(MipsSwitchFPState) .set hardfloat mfc0 t1, MIPS_COP_0_STATUS # Save old SR HAZARD_DELAY -#if defined(__mips_n64) +#if defined(__mips_n32) || defined(__mips_n64) or t0, t1, MIPS_SR_COP_1_BIT | MIPS_SR_FR # enable the coprocessor #else or t0, t1, MIPS_SR_COP_1_BIT # enable the coprocessor @@ -546,7 +546,7 @@ LEAF(MipsFPID) .set hardfloat mfc0 t1, MIPS_COP_0_STATUS # Save the status register. HAZARD_DELAY -#if defined(__mips_n64) +#if defined(__mips_n32) || defined(__mips_n64) or t0, t1, MIPS_SR_COP_1_BIT | MIPS_SR_FR #else or t0, t1, MIPS_SR_COP_1_BIT @@ -585,7 +585,7 @@ LEAF(MipsSaveCurFPState) PTR_L a0, TD_PCB(a0) # get pointer to pcb for thread mfc0 t1, MIPS_COP_0_STATUS # Disable interrupts and HAZARD_DELAY -#if defined(__mips_n64) +#if defined(__mips_n32) || defined(__mips_n64) or t0, t1, MIPS_SR_COP_1_BIT | MIPS_SR_FR # enable the coprocessor #else or t0, t1, MIPS_SR_COP_1_BIT # enable the coprocessor Modified: head/sys/mips/mips/trap.c ============================================================================== --- head/sys/mips/mips/trap.c Wed Jan 10 21:05:46 2018 (r327789) +++ head/sys/mips/mips/trap.c Wed Jan 10 21:08:43 2018 (r327790) @@ -983,7 +983,7 @@ dofault: addr = trapframe->pc; MipsSwitchFPState(PCPU_GET(fpcurthread), td->td_frame); PCPU_SET(fpcurthread, td); -#if defined(__mips_n64) +#if defined(__mips_n32) || defined(__mips_n64) td->td_frame->sr |= MIPS_SR_COP_1_BIT | MIPS_SR_FR; #else td->td_frame->sr |= MIPS_SR_COP_1_BIT;