Date: Sat, 12 Apr 1997 14:10:10 +0930 (CST) From: Michael Smith <msmith@atrad.adelaide.edu.au> To: spaz@u.washington.edu (John Utz) Cc: michaelh@cet.co.jp, avalon@coombs.anu.edu.au, terry@lambert.org, hackers@FreeBSD.org Subject: Re: 430TX ? Message-ID: <199704120440.OAA29855@genesis.atrad.adelaide.edu.au> In-Reply-To: <Pine.OSF.3.95.970411094154.31682B-100000@becker2.u.washington.edu> from John Utz at "Apr 11, 97 09:46:26 am"
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John Utz stands accused of saying: > > > > While we're talking about Intel, they claim that they're focusing more on > > memory bandwidth these days and the Pentium II has some kind of dual bus > > architecture that makes a significant performance difference. > > my instructor claims they separated the cache into instruction > cache and data-cache.....a previously 'discredited' architecture known to > the ancients as 'harvard architecture ( howard aiken )' as opposed to the > traditional 'von neumann' or 'princeton' architecture.... is cache space > relatively cheap these days? Split I&D cache is nothing 'discredited' (cf. Sparc, Mips, Motorola), and full-Havard CPUs have been around all along too (all of the m68k family, for example). Cache space has nothing to do with it; the basic idea is that code and data are not normally tightly mixed (instruction operands count as 'code') and thus having seperate caches for them can be a Good Thing. It Intel are hailing this as some sort of 'breakthrough', then that's just one more reason to laugh loudly at them. > John Utz spaz@u.washington.edu -- ]] Mike Smith, Software Engineer msmith@gsoft.com.au [[ ]] Genesis Software genesis@gsoft.com.au [[ ]] High-speed data acquisition and (GSM mobile) 0411-222-496 [[ ]] realtime instrument control. (ph) +61-8-8267-3493 [[ ]] Unix hardware collector. "Where are your PEZ?" The Tick [[
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